RISCV VERILOG HDL 代码 [英] RISCV VERILOG HDL code

问题描述

在 Xilinx ISE 上编译 RISCV VERILOG HDL 时出现以下错误:

I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE:

它说模块 vscale_pipeline 中第 296 行的以下代码中的不支持的系统函数调用"

It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline

295: ifndef SYNTHESIS
296: PC_WB <= $random;

推荐答案

一些综合工具定义了 SYNTHESIS 宏，以便使用

Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using

`ifdef SYNTHESIS
...
`endif

块，就像在这段代码中所做的那样.

blocks, as is done in this code.

Xilinx XST 默认不定义该宏，因此您必须手动配置 XST 以在综合期间定义宏.请参阅此 Xilinx AR，了解有关如何执行此操作的详细信息.

Xilinx XST does not define this macro by default, so you have to configure XST manually to define the macro during synthesis. See this Xilinx AR for details on how to do that.

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