阻塞赋值的左侧非法 [英] Illegal left hand side of blocking assignment

问题描述

我是 verilog 的新手.我正在编写 10x16 轮移位寄存器的代码.你能帮我解决这个错误吗，以及是否可以做任何优化?

I am new to verilog. I am writing the code for a 10x16 Round-Shift register. Can you help me with the error and also if any optimizations can be done?

module shift_reg_v(
    output [15:0] word_out
);

integer i;
integer j;

reg [159:0] coeff;
reg [15:0] word;

initial
begin
    for (i=0;i<160;i=i+1)
    begin   
        coeff[i] = 0;
    end

    for (i=0;i<16;i=i+1)
    begin   
        word[i] = 0;
    end
end

always
begin
for (j=0;j < 10;j = j+1)
begin
    for (i=0;i < 16;i = i+1)
    begin
        if (j==0)
        begin
            word[i] = coeff[(16*(j+1))+i];
        end
        else
        begin
            coeff[(16*j)+i] = coeff[(16*(j+1))+i];
        end
    end     
end

coeff[159:144] = word[15:0];
word_out[15:0] = word[15:0];

end
endmodule

程序在输出行显示 2 个错误:word_out[15:0] = word[15:0];

The program is showing 2 errors at the output line: word_out[15:0] = word[15:0];

推荐答案

参考错误:

错误-[IBLHS-NONREG] 左手边的非法行为a.sv, 42
非注册类型在此作业的左侧无效
违规表达是:word_out[15:0]
源信息:word_out[15:0] = word[15:0];

Error-[IBLHS-NONREG] Illegal behavioral left hand side a.sv, 42
Non reg type is not valid on the left hand side of this assignment
The offending expression is : word_out[15:0]
Source info: word_out[15:0] = word[15:0];

任何过程赋值语句的LHS必须是reg类型.过程赋值语句为 reg、integer、real 或 time 变量赋值，并且不能将值赋值给 <代码>电线.请注意，reg 可以根据某些触发事件保持或存储某些值，而 wire 不能存储任何值.

The LHS of any procedural assignment statement must be of reg type. Procedural assignment statements assign values to reg, integer, real, or time variables and can not assign values to wire. Note that reg can hold or store some value depending on some triggering event, while wire cannot store any value.

将 word_out 设为 reg 如下:

module shift_reg_v(
    output reg [15:0] word_out
);

参考警告:

警告-[PALF] 发现潜在的总是循环a.sv, 24
这个 always 块没有事件控制或延迟语句，它可能在模拟中导致无限循环.

Warning-[PALF] Potential always loop found a.sv, 24
This always block has no event control or delay statements, it might cause an infinite loop in simulation.

此外，您没有对always块执行给予任何敏感性.这可能会导致无限循环.always 块没有没有触发控制.此后该块将无限执行.

Moreover, you have not given any sensitivity for always block execution. This might result in infinite loop. There is no triggering control for always block. Henceforth the block shall execute infinitely.

使用 always @(*)(或 SystemVerilog 中的 always_comb)用于组合逻辑中的自动敏感度列表.

Use always @(*) (or always_comb in SystemVerilog) for automatic sensitivity list in combinational logic.

作为旁注，您可能有一个clk，作为模块的时钟输入，并使始终块在时钟边缘工作.这将有助于对时序逻辑进行建模.(注意在顺序逻辑的情况下使用非阻塞赋值 <=).

As a side note, you might have a clk, as clocking input to the module and make the always block work on the edge of clock. This will help in modelling sequential logic. (Note the usage of nonblocking assignments <= in case of sequential logic).

请参阅此 PDF 以了解 reg 和 nets 之间的区别.另外，这个 always block 可能有用.

Refer this PDF for difference between reg and nets.Also, this always block might be useful.

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