错误 VHDL Quartus:无法确定运算符“="的定义-- 找到 0 个可能的定义 [英] Error VHDL Quartus: can't determine definition of operator ""="" -- found 0 possible definitions

问题描述

我写了这个 vhdl 代码，但我有这个问题:

I write this vhdl code but I have this problems:

错误 (10327):CircuitoCombinatorio.vhd(16) 中的 VHDL 错误:无法确定运算符"="的定义——找到 0 个可能的定义.

Error (10327): VHDL error at CircuitoCombinatorio.vhd(16): can't determine definition of operator ""="" -- found 0 possible definitions.

行错误是:if(areset="1") then.

Line error is: if(areset="1") then.

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity CircuitoComparatore is
    port(a:in std_logic_vector(2 downto 0);
         clk,areset:in std_logic;
          u: out std_logic );
end CircuitoComparatore;

architecture ACircuitoComparatore of CircuitoComparatore is
    signal c,d: std_logic_vector(2 downto 0);
    begin
    c<=a+"011";
    reg:process(areset,clk)
        begin
        if(areset="1") then
            d<="000";
        elsif(ck'event and ck="1") then
            d<=c;
        end if;
    end process reg;
   CMP:process(a,d)
   begin
   if(a>d) then
        u<="001";
    else 
        u<="000";
    end if;
    end process CMP;
end ACircuitoComparatore;   

推荐答案

areset 是 std_logic 所以比较必须是 '1',不是 "1";下面也是一样，您可能希望将 ck 更改为 clk.

areset is std_logic so compare must be with '1', not "1"; same goes below, where you may want to change ck to clk.

下面的 u 也需要修复，它是 std_logic 但使用 "001" 分配了几个位.

Fix is also required for u below, which is std_logic but assigned with several bits using "001".

这篇关于错误 VHDL Quartus:无法确定运算符“="的定义-- 找到 0 个可能的定义的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！