如何在vhdl中使用sin，arcsin函数Quatus 2 16.1 Lite？ [英] How to use sin, arcsin functions in vhdl Quatus 2 16.1 Lite?

问题描述

我正在使用Quatus 2 Prime 16.1 Lite版本。

我正在尝试做如下操作，
我已经编译 float_pkg_c，fixed_pkg_c 在 ieee_proposed 库如下所示链接评论。我使用 to_float 将实变量转换为std逻辑向量，如下所示：

  phi_c< = to_std_logic_vector（to_float（phi_c_F，float32'high，-float32'low））; 
  

低于phi_c_F是一个变量，用math_real库的sin，arcsin计算， math_real非合成运算符，我想要xx.dddddddd 至少10个小数点。
然后，phi_c通过Avalon存储器映射（32位std逻辑向量）发送到HPS系统。

在下面的代码中，pre_digital，rp是整数，并且是在另一个进程中计算的信号。

  library ieee; 
 library ieee_proposed; 
 USE ieee.std_logic_1164.all; 
使用ieee.math_real.all; 
使用ieee.STD_LOGIC_ARITH.ALL; 
使用ieee.STD_LOGIC_UNSIGNED.ALL; 
使用ieee_proposed.float_pkg.ALL; 
使用ieee_proposed.fixed_pkg.ALL; 
使用ieee_proposed.fixed_float_types.ALL; 
  

内部架构，

  PROCESS（clk_50，start_cal）
变量Pr_F，rp_rad_s_F，F_c_F，ph_c_F，t_p_F，l_c_F，r_c_F，Ar_F，pre_R，r_s：float（4 downto -27）; 
 BEGIN 
 --r_s：= 8.98; 
 --r_c_F：= 3.44; 
 --l_c_F：= 5.67; 
 IF rising_edge（clk_50）AND start_cal ='1'THEN 
 
 pre_R：= to_float（pre_digital，4，27）; 
 Pr_F：= 3.3 *（pre_R / 65535.0）; 
 rpm_rad_s_F：= to_float（rp，4，27）*（2.0 * MATH_PI / 60.0）; 
 Ar_F：= MATH_PI * r_s * r_s; 
 F_c_F：= Pr_F * Ar_F; 
 ph_c_F：= arcsin（（r_c_F / l_c_F）* sin（rp_rad_s_F * to_float（t，4,27）））; 
 
 ph_c_F_vctr <= to_std_logic_vector（ph_c_F）; 
 END IF; 
 END PROCESS; 
  

在编译soc.system时出错，

错误（10511）：test_pipe.vhd（136）处的VHDL限定表达式错误：
Qualified Expression中指定的ARCSIN类型必须匹配
UNRESOLVED_float类型，根据你的代码和要求来判断，你似乎并不知道FPGA的功能。 FPGA由一系列可编程逻辑查找表组成，并结合一些硬连线乘法器。除了最新一代的Altera（Stratix 10）之外，这些乘法器仅仅是定点的，并且需要LUT中额外的逻辑来实现浮点类型的操作。另外，乘法器只能提供有限的精度：〜18位。

您似乎想要完整的浮点精度（64位），并执行非常复杂的操作，例如除法和三角函数函数（sin / arcsin）。实现这些功能需要很多的逻辑。三角函数甚至没有在 float_pkg 库中实现。你可能不得不使用类CORDIC组件来实现这样的功能。

但是想一想你想在你的代码中实现什么：

• 2 *浮点除法
  
• 8 *浮点乘法


• 1 * sin（）


• 1 * arcsin（）

>在一个时钟周期内！ clk_50 似乎表示50 MHz ...这不起作用。你需要正确地管理它。

你想在FPGA上实现的是先进的东西。你真的需要知道你在做什么。请简单地通过闪烁LED或其他东西来开始。

可能你应该在通用处理器上运行这个代码，而不是使用FPGA ...

I am using Quatus 2 Prime 16.1 Lite version.
what i am trying to do as follows, I have compiled float_pkg_c,fixed_pkg_c under ieee_proposed library as in shown in below link in comment. and i am using to_float to convert real variable to std logic vector as follows,

phi_c <= to_std_logic_vector( to_float(phi_c_F, float32'high, -float32'low) );

below phi_c_F is a variable which is to be calculated using sin, arcsin of math_real library.and i found operators in math_real non-synthesize, and i want there xx.dddddddd at least 10 decimal points. then, phi_c is send via Avalon memory mapping (32bits std logic vector) to HPS system.

in below code pre_digital,rp are integers and are signals which calculates in another process.

library ieee;
library ieee_proposed;
USE ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use ieee_proposed.float_pkg.ALL;
use ieee_proposed.fixed_pkg.ALL;
use ieee_proposed.fixed_float_types.ALL;

inside architecture,

PROCESS(clk_50,start_cal)
variable Pr_F,rp_rad_s_F,F_c_F,ph_c_F,t_p_F,l_c_F,r_c_F,Ar_F,pre_R ,r_s: float (4 downto -27); 
BEGIN
--r_s := 8.98;
--r_c_F := 3.44;
--l_c_F := 5.67;
IF rising_edge(clk_50)  AND start_cal ='1'  THEN

pre_R           := to_float(pre_digital,4 ,27) ;       
Pr_F            := 3.3 * (pre_R / 65535.0);    
rpm_rad_s_F     := to_float(rp,4 ,27) * (2.0 * MATH_PI / 60.0);
Ar_F            := MATH_PI*r_s*r_s;
F_c_F           := Pr_F * Ar_F;             
ph_c_F          := arcsin((r_c_F / l_c_F) * sin(rp_rad_s_F *  to_float(t,4 ,27)));

ph_c_F_vctr  <= to_std_logic_vector(ph_c_F);
END IF;
END PROCESS;    

when compiling soc.system i get error,

Error (10511): VHDL Qualified Expression error at test_pipe.vhd(136): ARCSIN type specified in Qualified Expression must match UNRESOLVED_float type that is implied for expression by context

解决方案

Judging by your code and requirements, it seems you are not aware of the capabilities of an FPGA. An FPGA consist of a collection of programmable logic lookup tables, combined with some hardwired multipliers. Except for the newest generation Altera (Stratix 10 e.g.), these multipliers are fixed-point only and would require extra logic in the LUTs to realize floating-point kind of operations. Also, the multipliers only offer limited precision: ~18 bit.

You seem to want full floating point precision (64 bit) and perform very complex operations, as division and trigonometric functions (sin/arcsin). A lot of logic is required to realize these functions. Trigonometric functions are not even implemented in the float_pkg library. You will probably have to use a CORDIC-like component to realize such a function.

But just think about what you seem to want to achieve in your code:

• 2 * floating-point division
• 8 * floating-point multiplication
• 1 * sin()
• 1 * arcsin()

All within one clock cycle! clk_50 seems to indicate 50 MHz... That's not going to work. You need to pipeline it properly.

What you want to realize on your FPGA is advanced stuff. You really need to know what you are doing. Please start simple, by flashing a LED or something.

Likely you should just run this code on a general purpose processor and not use an FPGA...

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