为什么“nop” arm编译器生成一种指令 [英] Why "nop" kind of instruction is generated by arm compiler

问题描述

签名char ch;

short int a = 220;



我已经返回上面的c程序来指定一个短的int签名字符如下。



ch = a; //将short int分配给signed char变量ch;



下面是为赋值语句生成的汇编代码。





MOV R2，R6，LSL 24 R6包含一个220

MOV R0，R0

MOV R2，R2， ASR 24

STRB R2，[SP，3]



我已经知道R6左移24位且Aritmetic右移24位来获取存储在堆栈中的有符号字节值。

但是我不明白为什么在两个MOV操作之间产生NOP类型的指令。

通常NOP指令用于在编程中引入一些延迟，等待某些操作完成。

但是这里为什么MOV R0，R0产生了什么意义呢？ br />


请一些人澄清。

解决方案

标志。

它清除了携带标志，以便它不会通过右移传播到结果值。

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/BABJAJIB.html [< a href =http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/BABJAJIB.html\"target =_ blanktitle =New Window> ^ ]

通常将nop指令引入已编译可执行文件的调试版本中：

1）对齐内部缓存结构的字节边界以获得更好的效果loading.

2）deb的占位符为调试器设置断点。

3）处理处理器上已知的时序问题。

如果目标处理器上没有实现NOP，它可能会这样做。请参阅此链接此处 [ ^ ]

signed char ch;
short int a = 220;

I have return the above c program to assign a short int to a signed char as below.

ch = a; //assigning short int to signed char variable ch;

Below is the assembly code generated for the assignment statement.


MOV R2, R6, LSL 24 R6 contain a which is 220
MOV R0, R0
MOV R2, R2, ASR 24
STRB R2,[SP,3]

I have understood that R6 is Left shifted by 24 bit and Aritmetic right shift by 24 bit to get the signed byte value which is stored in the stack.
But i don't understood why a NOP kind of instruction is generated in between the two MOV operaation.
Generally NOP instruction is used to introduce some delay in programming to wait until some operation has completed.
But here why MOV R0,R0 is generated what is the significance?

Please some one clarify.

解决方案

Flags.
It clears the Carry flag, so that it isn't propagated by the right shift into the resulting value.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/BABJAJIB.html[^]

Generally "nop" instructions are introduced into debug versions of the compiled executable for :
1) aligning to byte boundaries for internal cache structures for better loading.
2) a place holder for debugging breakpoints for debuggers.
3) handling known timing issues on processors.

If a NOP is not implemented on the target processor, it may do this. See this link here[^].

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