是否有必要由程序员显式地刷新写入组合存储器? [英] Is it necessary to flush write combine memory explicitly by programmer?

问题描述

我知道写组合写将被缓存，并且不会直接到达内存. 但是，程序员在其他人可以访问之前是否有必要显式刷新此内存?

I know that write combine writes will be cached, and don't reach the memory directly. But is it necessary for the programmer to flush this memory explicitly before others can access?

我从图形驱动程序代码中得到了这个问题.例如，CPU填充顶点缓冲区(映射为WC).但是在GPU访问它之前，我没有在代码中看到任何刷新操作. 架构(x86)是否已经为我们解决了这一问题?关于此的更多详细文档吗?

I got this question from the graphics driver code. For example, CPU fills the vertex buffer(mapped as WC). But before GPU access it, I don't see any flush operation in the code. Have the architecture(x86) already taken care of this for us? Any more detail document about this?

推荐答案

根据Intel®64和IA-32体系结构软件开发人员手册，卷3A:系统编程指南，第1部分(2012年8月版本，但这应该没有更改)，在第11.3.1节中，必须刷新缓冲区:

According to Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1 (August 2012 version, but this should not have changed), Section 11.3.1, the buffer must be flushed:

用于退出WC缓冲区的协议取决于实现，并且软件不应依赖该协议来实现系统内存一致性.使用WC内存类型时，软件必须对以下事实敏感:将数据写入系统内存的时间被延迟，并且在需要系统内存一致性时必须故意清空WC缓冲区.

The protocol for evicting the WC buffers is implementation dependent and should not be relied on by software for system memory coherency. When using the WC memory type, software must be sensitive to the fact that the writing of data to system memory is being delayed and must deliberately empty the WC buffers when system memory coherency is required.

如果图形驱动程序实际上并未刷新写合并缓冲区，则它们取决于系统特定的时序和/或缓冲区大小(同时假定后续的WC写操作将分配给该缓冲区，但从体系结构上不能保证).在普通的工作负载下，这可能会在现有系统上工作(或看起来可以工作)，但不能保证在体系结构上可以正常工作.

If the graphics drivers did not actually flush the write combining buffers, then they were depending on system specific timing and/or buffer sizes (while assuming that subsequent WC writes will be allocated to the buffer, this is not architecturally guaranteed). This may work (or appear to work) on existing systems under ordinary workloads, but it is not architecturally guaranteed to work.

由于各种各样的序列化事件将刷新写合并缓冲区，因此很可能存在刷新操作/事件，但并不明显(就像SFENCE一样).摘自《英特尔®64和IA-32体系结构软件开发人员手册》(版本052，2014年9月)，第3卷，第11.3节可用的缓存方法":

Since a broad range of serializing events will flush the write combining buffers, it is quite possible that the flush operation/event is present but not obvious (as an SFENCE would be). From Intel® 64 and IA-32 Architectures Software Developer’s Manual (version 052, September 2014), Volume 3, Section 11.3 Methods of Caching Available:

如果WC缓冲区被部分填充，则写入可能会延迟到下次发生序列化事件时；否则，写操作可能会延迟.例如SFENCE或MFENCE指令，CPUID执行，对未缓存的内存的读取或写入，中断发生或LOCK指令的执行.

If the WC buffer is partially filled, the writes may be delayed until the next occurrence of a serializing event; such as, an SFENCE or MFENCE instruction, CPUID execution, a read or write to uncached memory, an interrupt occurrence, or a LOCK instruction execution.

例如，对GPU寄存器的写操作(如果映射到未缓存的内存)将刷新写合并缓冲区.

For example, a write to a GPU register (if mapped to uncached memory) would flush the write combining buffer.

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