如何从预处理程序宏创建字符串 [英] How to create a string from a pre-processor macro

问题描述

我有一个预处理器宏，它代表设计中的分层路径.

I have a preprocessor macro that represents a hierarchical path into my design.

示例:

`define HPATH top.chip.block

我需要构造一个包含`HPATH值的字符串，因此在我的示例中，该字符串应等于top.chip.block.

I need to construct a string which holds the value of `HPATH, so in my example the string should equal top.chip.block.

有没有办法构造这样的字符串?

Is there a way to construct such a string?

以下尝试均无效:

string hpath;
hpath = "`HPATH";     // Results in hpath = "`HPATH"
hpath = \"``HPATH\";  // Doesn't compile
hpath = `HPATH;       // Doesn't compile

我希望hpath等同于执行此赋值hpath = "top.chip.block"，但是要使用`HPATH而不是再次指定路径.

I want hpath to be equivalent to doing this assignment hpath = "top.chip.block", but by using `HPATH instead of specifying the path again.

我不能使用%m，因为我需要在顶层UVM环境中而不是在模块中使用字符串.

I cannot use %m because I need the string within my top-level UVM environment, not within a module.

更多背景知识:之所以要这样做，是因为我在UVM类库中使用后门寄存器访问.后门API需要将hdl_path设置为设计中的块(以字符串形式).我已经对分层路径进行了定义，并在指定hdl_paths时尝试重用它们，因此我没有两次定义相同的路径.我的测试台将同时使用分层路径和字符串路径.

A little more background: the reason I want to do this is because I am using backdoor register access in the UVM class library. The backdoor API requires setting the hdl_path to the blocks within the design, as a string. I already have `defines for the hierarchical paths and am trying to reuse those when specifying the hdl_paths so I don't have the same path defined twice. My testbench will use both the hierarchical path and the string path.

推荐答案

在字符串文字中不能使用`define宏.根据SystemVerilog LRM:

It's not possible to use a `define macro within a string literal. According to the SystemVerilog LRM:

宏替换和参数替换不应在字符串文字中发生.

Macro substitution and argument substitution shall not occur within string literals.

但是，可以通过使用带有参数的宏来构造字符串文字，并通过使用''`将宏中的引号包括在内.

However a string literal can be constructed by using a macro that takes an argument and including the quotes in the macro by using ``"`.

同样，从LRM:

"会覆盖"的通常词汇含义，并表示扩展名应包含引号 标记，实际参数的替换以及嵌入式宏的扩展.这允许字符串文字为 由宏参数构造而成.

An `" overrides the usual lexical meaning of " and indicates that the expansion shall include the quotation mark, substitution of actual arguments, and expansions of embedded macros. This allows string literals to be constructed from macro arguments.

这可行:

`define STRINGIFY(x) `"x`"
`define HPATH top.chip.block
string hpath = `STRINGIFY(`HPATH);
$display(hpath);                       // Output: "top.chip.block"

示例代码可在此处运行: http://www.edaplayground.com/s/4/879

The example code can be run here: http://www.edaplayground.com/s/4/879

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