强制gnu make重建受编译器定义影响的对象 [英] Force gnu make to rebuild objects affected by compiler definition

问题描述

我有一个makefile文件，该文件在命令行中包含选项

I have a makefile that takes options at the command line

make OPTION_1=1

基于该值，它将向对象的子集添加其他编译器定义.

Based on the value it will add additional compiler definitions to a subset of objects.

ifeq ($(OPTION_1), 1)
CC_FLAGS += -DOPTION_1_ON
endif

定义的更改会影响所包含的头文件的内容-存根或实现暴露给目标文件.

The change in the definition affects the included header file content - a stub or an implementation is exposed to the object files.

如何通过此选项更改来重建受影响"的文件?

How can I get make to rebuild the files 'affected' by this option changing?

推荐答案

我使用文件来记住这些选项的最后一个值，例如:

I use a file to remember the last value of such options, like this:

.PHONY: force
compiler_flags: force
    echo '$(CC_FLAGS)' | cmp -s - $@ || echo '$(CC_FLAGS)' > $@

cmp || echo位表示仅在设置更改时才触摸文件compiler_flags，因此现在您可以编写类似

The cmp || echo bit means the file compiler_flags is only touched when the setting changes, so now you can write something like

$(OBJECTS): compiler_flags

每当编译器标志更改时，

都会导致重建$(OBJECTS).每次您运行make时，都会执行editor_flags的规则，但是，只有在实际修改了compiler_flags文件的情况下，才会触发$(OBJECTS)的重建.

to cause a rebuild of $(OBJECTS) whenever the compiler flags change. The rule for compiler_flags will be executed every time you run make, but a rebuild of $(OBJECTS) will be triggered only if the compiler_flags file was actually modified.

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