如何使用Makefile使用不同的CFLAGS编译不同的c文件? [英] How to compile different c files with different CFLAGS using Makefile?

问题描述

全部.假设我有一个程序，其中包含一长串C源文件，例如Ac，Bc，...，Zc，现在我想使用某些CFLAGS编译Ac，Bc，并使用其他CFLAGS编译源文件的其余部分CFLAGS值.

all. Let's say I have a program that contains a long list of C source files, A.c, B.c, ...., Z.c, now I want to compile A.c, B.c with certain CFLAGS, and compile the rest part of source files with a different CFLAGS value.

如何编写Makefile来完成上述工作?当前我在Makefile中正在做的是:

How to write a Makefile to do the above described job? currently what I am doing in my Makefile is:

OBJ=[all other .o files here, e.g. D.o, D.o, E.o .... Z.o]
SPECIAL_OBJS=A.o B.o

all: $(OBJ) $(SPECIAL_OBJS)

$(SPECIAL_OBJS): 
     @echo [Compiling]: $(@:.o=.c)
     $(CC) [SOME OTHER GCC OPTIONS HERE] $(CFLAGS) -c $(@:.o=.c) -o $@

%.o: %.c
     @echo [Compiling]: $<
     $(CC) $(CFLAGS) -o $@ -c $<

它可以工作，但看起来只是愚蠢/复杂.任何人都可以帮助指出在Makefile中执行此操作的推荐方法吗?谢谢！

It works, but looks just stupid/complicated. Can anyone help to point out what is the recommended way of doing this in Makefile? thanks!

推荐答案

尝试使用特定于目标的变量.特定于目标的变量声明如下:

Try using target-specific variables. A target-specific variable is declared like this:

TARGET: VAR := foo  # Any valid form of assignment may be used ( =, :=, +=, ?=)

现在，当创建名为TARGET的目标时，名为VAR的变量将具有值"foo".

Now when the target named TARGET is being made, the variable named VAR will have the value "foo".

使用特定于目标的变量，您可以这样做，例如:

Using target-specific variables, you could do this, for example:

OBJ=[all other .o files here, e.g. D.o, D.o, E.o .... Z.o]
SPECIAL_OBJS=A.o B.o

all: $(OBJ) $(SPECIAL_OBJS)

$(SPECIAL_OBJS): EXTRA_FLAGS := -std=c99   # Whatever extra flags you need

%.o: %.c
     @echo [Compiling]: $<
     $(CC) $(CFLAGS) $(EXTRA_FLAGS) -o $@ -c $<

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