makefile相对路径是否与gcc相对路径相同? [英] Are makefile relative paths treated the same as gcc relative paths?

问题描述

我知道这听起来像是一个愚蠢的问题，确实如此.我正在尝试编写一个makefile，该文件将针对我正在编写的静态库(这是一个单元测试框架)进行构建和链接.基本上，当我使用make时，我不知道gcc调用的工作目录在哪里.

I know this sounds like a stupid question, and it is. I'm trying to write a makefile, which builds and links against a static library that I'm writing (this is a unit testing framework). Basically I can't figure out where the working directory of the call to gcc is when I use make.

我的目录结构如下:

./
|-> src
|-> include
|-> project
    |-> Makefile
|-> test
    |-> test.c, test.h
    |-> project
        |-> Makefile

因此，如果我进入test/project目录并键入以下命令，则似乎没有任何问题

So, if I go to the test/project directory and type the following command, I don't seem to have any problems

gcc -I../../include -I../../src ../test.c

但是，如果我使用配置基本相同的makefile(makefile在下面)，则会在以下方面出现错误:

But if I use a makefile with essentially the same configuration (makefile is below), then I get an error along the lines of:

gcc -o test ../test.c
In file included from ../test.c:7:0:
../test.h:8:24: fatal error: System.h: No such file or directory
#include "System.h"

(System.h是我位于include/目录的头文件之一).

(System.h is one of my header files located in the include/ directory).

这是我的问题.由于我正在尝试使用gcc在与makefile不同的相对路径下编译文件，makefile包含与自身不同的相对路径，因此使用make执行此操作的正确方法是什么?我应该将工作目录更改为包含test.c的目录，并包含相对于该目录的目录，还是应该为所有内容都放置相对路径，就像我从makefile目录中调用gcc一样?

So here's my question. Since I'm trying to use gcc to compile a file at a different relative path from the makefile, which has includes from a different relative path from itself, what is the proper way to do this with make? Should I change my working directory to the one that contains test.c, and include relative to that directory, or should I put relative paths to everything as if I called gcc from the directory of the makefile?

这是我的makefile文件

Here's my makefile

CC = gcc
CFLAGS = -Wall -std=c99 -static -I../../include -I../../src -L$(LIBTARGET) -lmystaticlib
TARGET_APP=test
LIBTARGET = ../../project

all : $(TARGET_APP)

$(TARGET_APP) : library
        $(CC) ${CLAGS} -o $@ ../test.c

library : 
        $(MAKE) -C $(LIBTARGET)

推荐答案

在makefile中将${CLAGS}替换为$(CFLAGS)(用括号代替括号，在变量名中键入错误).现在，不使用makefile中的CFLAGS变量.这是其内容未出现在编译器调用中的原因，也是../../include不在编译器搜索路径中的原因.

Replace ${CLAGS} with $(CFLAGS) (parens instead of brackets, fix typo in variable name) in the makefile. As it is now, the CFLAGS variable in the makefile is not used. That is the reason that its contents don't show up in the compiler call, and that is the reason that ../../include is not part of the compiler search path.

除此之外:除非您进行了一些更改，否则编译器调用的工作目录就是您从中调用make的目录.您可以通过放置一个包含以下内容的makefile进行测试:

Other than that: Unless you did something to change it, the working directory of the compiler call is the directory from which you called make. You can test this by putting a makefile with the following contents:

all:
        pwd

在目录中，例如说/home/user/foo/bar/Makefile.然后:

in a directory, say /home/user/foo/bar/Makefile. Then:

$ cd /home/user/foo/bar
$ make
/home/user/foo/bar
$ cd ..
$ make -f bar/Makefile
/home/user/foo

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