命令行中的Makefile和变量目标 [英] Makefile and variable target from command line

问题描述

关于Makefile的新手问题...为什么不起作用?

Newbie question for Makefiles... why doesn't this work?

TARGET=$@

$(TARGET): * **/*
    @echo "TARGET=$(TARGET)"

这在哪里?

TARGET=my_target

$(TARGET): * **/*
    @echo "TARGET=$(TARGET)"

从make my_target开始时是什么?

前者的结果是，没有规则将目标设为"my_target"."

Result of the former is, "no rule to make target `my_target'."

除了为什么这不起作用"这个问题之外，还有其他解决方法吗?我希望能够从命令行指定任意目标.我想我可以对一个env var做出反应，但这会使CLI显得笨拙，例如make target=my_target build或类似的

In addition to the question "why this doesn't work," is there a workaround? I'd like to be able to specify an arbitrary target from the command line. I suppose I could react to an env var, but that makes the CLI clunky, e.g., make target=my_target build or similar.

我已经搜索过，但无法获得正确的结果来解决此问题. GNU使3.81.谢谢！

I've searched, but I'm not getting the right hits to solve this. GNU make 3.81. Thanks!

推荐答案

自动变量$@是在模式规则的上下文中定义的；没有任何规则.

The automatic variable $@ is defined in the context of a pattern rule; outside of any rule it has no value.

如果您希望Make对您要命名的目标做同样的事情，则可以使用任何匹配规则:

If you want Make to do the same thing to whatever target you name, you can use a match-anything rule:

%:
    @echo TARGET=$@

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