在Makefile中导出变量 [英] Export variable in Makefile

问题描述

在我的makefile中导出变量时出现问题.我在/home/user/sarwan/DMAgent目录中有Makefile.mk.

Having problem in exporting a variable in my makefile. I have Makefile.mk in /home/user/sarwan/DMAgent directory.

我有以下声明:

export VZW_BASE_DIR=$(PWD)

然后我在/home/user/sarwan/DMAgent/agent目录中还有另一个makefile，其中包含:

Then I have another makefile in /home/user/sarwan/DMAgent/agent directory which contains:

include ../Makefile.mk
export VZW_BASE_DIR

问题是我希望VZW_BASE_DIR是/home/user/sarwan/DMAgent，而是将其作为 /home/user/sarwan/DMAgent/agent.

Problem is I expect VZW_BASE_DIR to be /home/user/sarwan/DMAgent but rather its taking as /home/user/sarwan/DMAgent/agent.

我该如何编写以使其按预期工作?

How can I write so that it works as expected?

推荐答案

PWD为您提供当前的工作目录，而不是当前包含的文件所在的目录.即使将文件包含在完全不同的目录中，您的工作目录保持不变.

PWD gives you your current working directory, not the directory the currently included file is in. Even when including a file in a totally different directory, your working directory stays the same.

由于您已经已经对相对路径进行了硬编码(请参见include语句)，因此我认为继续这样做不会有其他原因.首先，生成目录中的makefile:

Since you're already hard-coding relative paths (see the include statement), I see no issue with continuing to do so for other reasons. First, the makefile in your build directory:

export REL_DIR=..
include $(REL_DIR)/Makefile.mk

然后，在您包含的makefile中:

Then, in your included makefile:

export VZW_BASE_DIR=$(PWD)/$(REL_DIR)

这将限制您必须对一个位置(REL_DIR的设置)进行更改的范围.然后，它使用该变量来引用包含的文件和设置基本目录.

This limits the scope of changes you have to make to one location, the setting of REL_DIR. It then uses that variable to both reference the included file and set the base directory.

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