如何在Verilog编码中找到MAX或MIN? [英] How to find MAX or MIN in Verilog coding?

问题描述

问题很简单，我听说assign out = (a>b)?a:b是错误的.这是错的吗?如果是的话，还有其他方法可以找到MAX吗?

the question is simple, I heared that assign out = (a>b)?a:b is wrong. is it wrong? if it is, is there another way to find MAX?

推荐答案

当且仅当out是wire时才是正确的.如果是寄存器，则必须执行以下操作:

It's right if and only if out is a wire. If it's a register, then you have to do something like this:

always @* begin
  if (a>b)
    out = a;
  else
    out = b;
end

请注意，在Verilog中，类型为reg的变量可以推断导线或锁存器或真实寄存器.这取决于您如何指定使用该reg的模块的行为:

Take into account that in Verilog, a variable of type reg can infer either a wire or a latch, or a true register. It depends on how you specify the behaviour of the module that uses that reg:

组合(out是wire，但它是reg)

module max (input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @* begin
    if (a>b)
      out = a;
    else
      out = b;
  end
endmodule

组合国民(out被实现为wire，并且被定义为wire)

Combinational (out is implemented as a wire and it's defined as a wire)

module max (input [7:0] a, 
            input [7:0] b, 
            output [7:0] out);
  assign out = (a>b)? a : b;
endmodule

锁存器(out是reg，它实现为锁存器，如果条件不变，则存储最后产生的结果，即如果a==b(顺便说一句)可能无法提供正确的输出在这种情况下)

Latch (out is a reg, and it's implemented as a latch which stores the last produced result if conditions don't make it change, i.e. if a==b, which btw, may not provide a correct output in that case)

module max (input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @* begin
    if (a>b)
      out = a;
    else if (a<b)
      out = b;
  end
endmodule

寄存器(out被实现为真正的寄存器，时钟沿被触发)

Register (out is implemented as a true register, clock edge triggered)

module max (input clk,
            input [7:0] a, 
            input [7:0] b, 
            output reg [7:0] out);
  always @(posedge clk) begin
    if (a>b)
      out <= a;
    else if (a<=b)
      out <= b;
  end
endmodule

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