为什么x86丑陋?与其他人相比,为什么它被认为是次等的? [英] Why is x86 ugly? Why is it considered inferior when compared to others?

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问题描述

最近,我一直在阅读一些SO档案,并遇到了针对x86体系结构的声明.

以及更多类似的评论

我尝试搜索,但没有找到任何原因.我认为x86不错,可能是因为这是我所熟悉的唯一体系结构.

有人能给我理由比其他人认为x86丑陋/不好/劣等吗.

解决方案

可能的原因:

  1. x86是一个相对较旧的 ISA (毕竟其祖先是8086年代)
  2. >
  3. x86已经发展了数倍,但是需要硬件来保持与旧二进制文件的向后兼容性.例如,现代的x86硬件仍然支持本地运行16位代码.此外,存在几种内存寻址模型,以允许较旧的代码在同一处理器上进行互操作,例如实模式,保护模式,虚拟8086模式和(amd64)长模式.这可能会使某些人感到困惑.
  4. x86是CISC机器.长期以来,这意味着它比MIPS或ARM等RISC机器要慢,因为指令具有数据相互依赖性和标志指令级并行性的形式难以实现.现代实现将x86指令转换为RISC下的类似RISC的指令,称为" micro-ops .涵盖使这些优化在硬件中切实可行的实现方式.
  5. 在某些方面,x86并不逊色,只是有所不同.例如,输入/输出在绝大多数体系结构上都作为内存映射来处理,而在x86上则不这样. (注意:现代的x86机器通常具有某种形式的 DMA 支持,并通过内存与其他硬件进行通信映射;但是 ISA 仍具有I/O指令,例如INOUT)
  6. x86 ISA 具有很少的体系结构寄存器,这可以迫使程序往返通过内存比其他方式更频繁地访问内存.尽管高效的存储转发,但是执行此操作所需的额外指令会占用可能用于有用工作的执行资源. 保持较低的延迟.将寄存器重命名为大型物理寄存器文件的现代实现可以使许多指令保持运行状态,但是缺少体系结构寄存器仍然是32位x86的一个显着弱点. x86-64的整数从8增加到16,向量寄存器是64位代码快于32位(以及更有效的寄存器调用ABI)的最大因素之一,而不是每个寄存器的宽度增加.从16个整数寄存器进一步增加到32个整数寄存器将有所帮助,但效果不尽如人意. (但是,由于浮点代码具有更高的延迟并且通常需要更多的常量,因此AVX512确实增加了32个向量寄存器.)( MOVSB指令需要相对较大的C代码块描述它的作用:

    if (DF==0) 
      *(byte*)DI++ = *(byte*)SI++; 
    else 
      *(byte*)DI-- = *(byte*)SI--;
    

    那是一条执行加载,存储和两条加法或减法(由标志输入控制)的指令,每条指令在RISC机器上都是单独的指令.

    虽然MIPS(和类似的体系结构)的简单性并不一定会使它们更胜一筹,但对于讲解汇编程序类的入门知识而言,从更简单的 y86 ,该子集已被简化为对于实际使用很有用(例如,没有移位指令),或者有些只教授基本的x86指令.

  7. x86使用可变长度的操作码,这会增加指令解析方面的硬件复杂性.在现代时代,由于CPU受内存带宽的限制越来越多,而不是受原始计算的限制,因此这种成本正变得越来越小,但是许多"x86扑朔迷离"的文章和态度都来自这个成本相对要大得多的时代.
    2016年更新:Anandtech发布了有关x64下操作码大小的讨论和AArch64 .


这不应该是x86的重击!派对.考虑到问题的措辞方式,我别无选择,只能做一些扑朔迷离的事情.但是,除了(1)以外,所有这些操作都是有充分理由的(请参见注释).英特尔设计师并不愚蠢-他们想通过自己的体系结构来实现某些目标,而这些正是为使这些目标变为现实而必须支付的一些税金.

Recently I've been reading some SO archives and encountered statements against the x86 architecture.

and many more comments like

I tried searching but didn't find any reasons. I don't find x86 bad probably because this is the only architecture I'm familiar with.

Can someone kindly give me reasons for considering x86 ugly/bad/inferior compared to others.

解决方案

Couple of possible reasons for it:

  1. x86 is a relatively old ISA (its progenitors were 8086s, after all)
  2. x86 has evolved significantly several times, but hardware is required to maintain backwards compatibility with old binaries. For example, modern x86 hardware still contains support for running 16 bit code natively. Additionally, several memory-addressing models exist to allow older code to inter-operate on the same processor, such as real mode, protected mode, virtual 8086 mode, and (amd64) long mode. This can be confusing to some.
  3. x86 is a CISC machine. For a long time this meant it was slower than RISC machines like MIPS or ARM, because instructions have data interdependency and flags making most forms of instruction level parallelism difficult to implement. Modern implementations translate the x86 instructions into RISC-like instructions called "micro-ops" under the covers to make these kinds of optimizations practical to implement in hardware.
  4. In some respects, the x86 isn't inferior, it's just different. For example, input/output is handled as memory mapping on the vast majority of architectures, but not on the x86. (NB: Modern x86 machines typically have some form of DMA support, and communicate with other hardware through memory mapping; but the ISA still has I/O instructions like IN and OUT)
  5. The x86 ISA has a very few architectural registers, which can force programs to round-trip through memory more frequently than would otherwise be necessary. The extra instructions needed to do this take execution resources that could be spent on useful work, although efficient store-forwarding keeps the latency low. Modern implementations with register renaming onto a large physical register file can keep many instructions in flight, but lack of architectural registers was still a significant weakness for 32-bit x86. x86-64's increase from 8 to 16 integer and vector registers is one of the biggest factors in 64bit code being faster than 32-bit (along with the more efficient register-call ABI), not the increased width of each register. A further increase from 16 to 32 integer registers would help some, but not as much. (AVX512 does increase to 32 vector registers, though, because floating-point code has higher latency and often needs more constants.) (see comment)
  6. x86 assembly code is complicated because x86 is a complicated architecture with many features. An instruction listing for a typical MIPS machine fits on a single letter sized piece of paper. The equivalent listing for x86 fills several pages, and the instructions just do more, so you often need a bigger explanation of what they do than a listing can provide. For example, the MOVSB instruction needs a relatively large block of C code to describe what it does:

    if (DF==0) 
      *(byte*)DI++ = *(byte*)SI++; 
    else 
      *(byte*)DI-- = *(byte*)SI--;
    

    That's a single instruction doing a load, a store, and two adds or subtracts (controlled by a flag input), each of which would be separate instructions on a RISC machine.

    While MIPS (and similar architectures) simplicity doesn't necessarily make them superior, for teaching an introduction to assembler class it makes sense to start with a simpler ISA. Some assembly classes teach an ultra-simplified subset of x86 called y86, which is simplified beyond the point of not being useful for real use (e.g. no shift instructions), or some teach just the basic x86 instructions.

  7. The x86 uses variable-length opcodes, which add hardware complexity with respect to the parsing of instructions. In the modern era this cost is becoming vanishingly small as CPUs become more and more limited by memory bandwidth than by raw computation, but many "x86 bashing" articles and attitudes come from an era when this cost was comparatively much larger.
    Update 2016: Anandtech has posted a discussion regarding opcode sizes under x64 and AArch64.


EDIT: This is not supposed to be a bash the x86! party. I had little choice but to do some amount of bashing given the way the question's worded. But with the exception of (1), all these things were done for good reasons (see comments). Intel designers aren't stupid -- they wanted to achieve some things with their architecture, and these are some of the taxes they had to pay to make those things a reality.

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