您如何在Python中模拟硬件? [英] How do you simulate hardware in Python?

问题描述

那种令人困惑的标题，但是我的任务是用高级语言(我可能最了解python)编写一个4级MIPS处理器(IF，ID，EX，WB).除了我什至尚未开始尝试的有关缓存和停顿的困难之外，如何处理应该并行运行的代码并使之顺序运行?考虑一下此代码段.

Kind of confusing title but my assignment is to write a 4 stage MIPS processor (IF, ID, EX, WB) in a high level language (I know python best probably). Beyond the difficulty I haven't even started to try yet of caches and stalls, how do you take code that is supposed to be running in parallel and make that sequential? Consider this code snippit.

pc = 0x0
IFinput, IDinput, EXinput, WBinput = None, None, None, None
while True:
    IFinput = self.memory.getInstruction(pc)
    if not IFinput: #No more instructions
        break

    self.IF.giveInput(IFinput)
    self.ID.giveInput(IDinput)
    self.EX.giveInput(EXinput)
    self.WB.giveInput(WBinput)

    instruction += 0x4
    clock += 1

    IDinput = self.IF.getOutput(clock)
    EXinput = self.ID.getOutput(clock)
    WBinput = self.EX.getOutput(clock)
    result  = self.WB.getOutput(clock)
result.printToFile()

我正在尝试将事物的输入和输出分为两个不同的阶段，以便在执行"clock + = 1"命令之前，不要通过取回输出来欺骗"硬件.这是实现此目标的正确方法吗?是否编写了适合该任务的python库?谢谢.

I'm trying to break apart the input and output of the thing into two different stages such that I dont "cheat" the hardware by getting output back before the "clock += 1" command executes. Is that the right way to implement this? Are there any python libraries that were written that are suited to this task? Thanks.

推荐答案

考虑特定于目的的语言，例如VHDL或Verilog；可能带有组合/扩展名，例如 PyHVL 或

Consider purpose-specific languages like VHDL or Verilog; possibly with a combination/extension such as PyHVL or Cocotb ..

..但是，如果必须从头开始和/或使用纯Python实现创建此 ，请考虑使用与高级硬件语言相同的概念.特别地，考虑一个 active 设计. Verilog和VHDL都支持此概念-输入的更改(例如时钟)驱动行为和新的输出状态.

.. however, if this must be created from scratch and/or a pure-Python implementation, consider using the same concepts as in the high-level hardware languages. In particular, consider a reactive design. Both Verilog and VHDL support this notion - where a change to input, such as the clock, drives the behaviors and new output state.

每个反应性回调"然后简单地进入输入状态并发出与其他组件隔离的特定输出状态.然后通过状态更改和围绕更改的反应性触发器仅来建立依赖关系.

Each "reactive callback" then simply takes in the input state and emits a particular output state in isolation from the other components. Dependencies are then established only by state changes and reactive triggers around changes.

触发器/防护中可能使用的东西:

Things that might be used in triggers/guards:

• 行或数据更改状态
• 发信号事件
• 周期计数(例如最小，之后，随机)

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