MIPS中的Rem和MFHI之间的区别 [英] Difference between rem and mfhi in MIPS

问题描述

这之间有什么区别吗?

rem $s0, $t0, $t1

和这个:

div $t0, $t1
mfhi $s0

我知道第一个可以使用，但是我不确定第二个可以使用.是同一回事吗?

I know that the first one works but I'm not sure about the second. Is it the same thing?

推荐答案

较早的MIPS没有rem，只有一个div可以将结果放入特殊寄存器中，以避免回写到主寄存器时的微体系结构问题.通过简单的流水线从高延迟指令中注册文件.

older MIPS didn't have rem, only a div that put the results into special registers, to avoid microarchitectural problems with write-back to the register file from a high latency instruction in a simple pipeline.

不是mfhi计算余数，而是div(在lo=quotient和hi=remainder特殊寄存器中产生结果). mfhi只是从HI移动"；它将从该特殊寄存器复制到通用寄存器.

It's not the mfhi that's computing the remainder, it's div (producing its result in the lo=quotient and hi=remainder special registers). mfhi is just "Move from HI"; it copies from that special register to a general-purpose register.

名称来自mult指令(与add相比，其延迟要长于add或原始MIPS I支持的任何其他整数ALU指令)，这会在LO和HI中产生双倍宽度的结果. (从mult的mips中获取结果和 在MIPS中，什么是HI和LO ).

The names come from the mult instruction (which like div has higher latency than add or any other integer ALU instruction supported by original MIPS I), which produces a double-width result in LO and HI. (Getting result from mult in mips and In MIPS, what is HI and LO).

如果mult和div的目的地是通用寄存器，则在循环中结果准备就绪，可能还会有add或lw或管道需要执行的其他任何结果在同一周期内写入寄存器文件.这些指令每个产生2个字的结果.使用特殊的LO/HI寄存器可避免两种原因的回写冲突.

If the destinations of mult and div were general-purpose registers, then in the cycle the results were ready, there might also be an add or lw or whatever other result that the pipeline needed to write to the register file in the same cycle. And those instructions produce 2 word results each. Using special LO/HI registers avoids write-back conflicts from both causes.

还请记住，MIPS代表最小程度互锁的管线阶段"，因此早期MIPS的主要设计目标是甚至没有硬件来检查数据依赖性，而将其留给软件，以便在准备好结果之前不要尝试读取结果.将mult/mfhi/mflo特殊化也可以帮助解决这一问题，因为普通GP寄存器没有依赖性.

Also remember that MIPS stands for Minimally Interlocked Pipeline Stages, so a major design goal for early MIPS was to not have hardware even check for data dependencies, and leave that up to software to not try to read a result before it was ready. Making mult / mfhi / mflo special also helps with that, because there isn't a dependency through a normal GP register.

但是，更现代的MIPS CPU具有更大的晶体管预算，并且可以支持mul和rem这样的指令，即使它们的延迟比普通的ALU指令更长，也可以将其结果存储在GP寄存器中.

But more modern MIPS CPUs have a much larger transistor budget, and can support instructions like mul and rem that put their results in GP registers even though they have higher latency than normal ALU instructions.

我不确定何时将它们添加到ISA中.那是否处于r10000之类的高性能乱序执行MIPS CPU的时代.

I'm not sure when they were added to the ISA; whether that was in the era of high-performance out-of-order execution MIPS CPUs like r10000.

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