单线程在多核处理器上的数据可见性 [英] Data visibility on multi-core processor by single thread

问题描述

在单线程程序中，如何将内核1中的线程所做的更改显示给另一个内核2，以便在上下文切换之后，该线程(现在在内核2上运行)将具有更新的值?

In a single thread program, how are changes made by thread in core 1 made visible to another core 2, so that after a context switch the thread (now running on core 2) will have updated value?

请考虑以下示例:

1. 主存储器中变量x的值为10.

该线程在内核1上运行，并将x更改为5，由于我们未使用任何内存屏障，该线程仍在缓存中并且尚未刷新到主内存.

The thread runs on core 1 and changes x to 5, which is still in cache and not yet flushed to main memory as we are not using any memory barrier.

发生上下文切换，并且线程从核心1移动到核心2.

A context switch occurs and the thread moves from core 1 to core 2.

线程读取x的值.

如果上下文切换后线程在内核2中恢复执行，x的值是什么?

What would be the value of x if thread resumes execution in core 2 after the context switch?

如果缓存一致性"通过管理一致性来处理上述情况，那么为什么在多线程程序中需要显式锁定(或任何读/写屏障)?

If "cache coherence" manages consistency to handle a case like above then why do we need for explicit locking (or any read/write barrier) in a multi-threaded program?

推荐答案

考虑到您的第一个问题，上下文切换还保留寄存器内容.因此，即使移至另一个内核(或CPU)，线程也会看到最新的值.

Considering your first question, context switches also preserve the register contents. Therefore, the threads sees the latest value, even if moved to another core (or CPU).

但是对于多线程程序，CPU 寄存器对于不同的线程是不同的(无论执行了多少 core 个线程)，并且寄存器不属于缓存一致性.

However for a multi-threaded program, CPU registers are distinct for different threads (regardless on how many cores the threads are executed), and registers are not part of cache coherency.

因此，我认为，多线程程序确实需要确保寄存器中的值与主存储器中的值是最新的. (缓存一致性仅确保CPU缓存与内存保持最新). 因此，我想，您需要一个屏障来使寄存器与内存同步.

Therefore, I think, a multi-threaded program does need to make sure the values in the registers are up-to-date with the values in the main memory. (Cache coherence only makes sure that the CPU cache is up-to-date with the memory). Therefore, I suppose, you need a barrier to synchronize the register with the memory.

您可以这样理解:该程序实际上仅在主存储器上运行.但是，编译器会优化对主内存的访问，并使用寄存器进行中间操作. 因此，程序仅访问存储器和寄存器. 但是，CPU还引入了自己的内存 cache . 高速缓存在内部(由CPU)优化对内存的读写操作. 缓存一致性仅确保CPU内的缓存是最新的(因此，访问内存的程序将获得正确的值.)

You can understand it as this: the program essentially operates only on the main memory. However, compilers optimise access to main memory and use registers for intermediate operations. Thus, the program access only memory and registers. However, the CPU also introduces its own cache of the memory. Reads and writes from/to the memory are internally (by the CPU) optimised by the cache. Cache coherency only ensures within the CPU, that the cache is up-to-date (and therefore, a program accessing memory gets the correct value.)

总结:

• 缓存一致性确保缓存和内存是最新的，因为它不受程序的控制在CPU内部.
• 上下文切换由操作系统处理，当将线程移动到不同的内核时，它可以确保寄存器的正确值.
• 内存障碍确保寄存器和内存是最新的，这是程序必须确保的.

• Cache coherence ensures cache and memory are up-to-date, it is out of the control of the program, as it is internal to the CPU.
• Context switches are handled by the operating system, which ensures correct values of registers when it moves threads to different cores.
• Memory barriers ensure that the registers and memory are up-to-date, this is what the program has to ensure.

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