虚拟索引的物理标记的缓存 [英] Virtually indexed physically tagged cache Synonym

问题描述

我无法完全掌握VIPT缓存中的同义词或别名的概念.

I am not able to entirely grasp the concept of synonyms or aliasing in VIPT caches.

将地址拆分为:-

在这里，假设我们有2个页面，其中不同的VA映射到相同的物理地址(或帧号).

Here, suppose we have 2 pages with different VA's mapped to same physical address(or frame no).

不同的VA的 pageno部分(位13-39)被转换为PA的 PFN (位12-35)，并且两者的PFN均相同VA映射到相同的物理帧.

The pageno part of VA (bits 13-39) which are different gets translated to PFN of PA(bits 12-35) and the PFN remains same for both the VA's as they are mapped to same physical frame.

现在，两个VA的 pageoffset 部分(位0-13)与它们要从特定帧访问的数据相同(不相同).

Now the pageoffset part(bits 0-13) of both the VA's are same as the data which they want to access from a particular frame no is same.

由于两个VA的 pageoffset部分相同，位(5-13)也将相同，因此索引或设置为no 相同，因此存在应该是没有别名，因为只有单个集合或索引号被映射到物理帧号.

As the pageoffset part of both VA's are same, bits (5-13) will also be same, so the index or set no is the same and hence there should be no aliasing as only single set or index no is mapped to a physical frame no.

图中的第12位如何负责混叠?我不明白.

How is bit 12 as shown in the diagram, responsible for aliasing ? I am not able to understand that.

如果有人可以在地址的帮助下举一个例子，那就太好了.

It would be great if someone could give an example with the help of addresses.

谢谢.

推荐答案

页面偏移量是0-11位，而不是0-13位.看一下底部的图:页面偏移量是低12位，因此您有4k页面(如x86和其他常见体系结构).

The page offset is bits 0-11, not 0-13. Look at your bottom diagram: the page offset is the low 12 bits, so you have 4k pages (like x86 and other common architectures).

如果任何索引位来自页面偏移量以上，VIPT的行为将不再像PIPT那样具有对索引位的自由转换.就是这种情况.

If any of the index bits come from above the page offset, VIPT no longer behaves like a PIPT with free translation for the index bits. That's the case here.

一个进程可以将相同的物理页面(框架)映射到2个不同的虚拟页面.

A process can have the same physical page (frame) mapped to 2 different virtual pages.

您声称​​不同的VA(第13-39位)的分页部分被转换为PA的PFN(第12-35位)，并且两个VA的PFN保持不变是完全相同的虚假.翻译可以更改第12位. 因此，其中一个索引位实际上是虚拟的，而不是物理的，因此同一物理行的两个条目可以进入不同的集合.

Your claim that The pageno part of VA (bits 13-39) which are different gets translated to PFN of PA(bits 12-35) and the PFN remains same for both the VA's is totally bogus. Translation can change bit #12. So one of the index bits really is virtual and not also physical, so two entries for the same physical line can go in different sets.

我认为我的主要困惑是关于页面偏移范围. PA和VA是否相同(即0-11)还是VA是0-12，PA是0-11?他们会永远一样吗?

I think my main confusion is regarding the page offset range. Is it the same for both PA and VA (that is 0-11) or is it 0-12 for VA and 0-11 for PA? Will they always be same?

PA和VA始终相同.页面偏移量未在图表的VA部分标记，仅将位的范围用作索引.

It's always the same for PA and VA. The page offset isn't marked on the VA part of your diagram, only the range of bits used as the index.

它没有任何区别是没有意义的:虚拟和物理内存都是字节可寻址的(或字可寻址的).当然，页面框架(物理页面)的大小与虚拟页面的大小相同.在从虚拟到物理的转换过程中，将地址右移或左移都没有意义.

It wouldn't make sense for it to be any different: virtual and physical memory are both byte-addressable (or word-addressable). And of course a page frame (physical page) is the same size as a virtual page. Right or left shifting an address during translation from virtual to physical would make no sense.

如评论中所述:

我最终找到了 http://www.cse.unsw.edu.au/~cs9242/02/lectures/03-cache/node8.html (其中包含图中的问题！).它说的是同一件事:物理标记确实解决了缓存同音异义问题，作为上下文切换刷新的替代方法.

I did eventually find http://www.cse.unsw.edu.au/~cs9242/02/lectures/03-cache/node8.html (which includes the diagram in the question!). It says the same thing: physical tagging does solve the cache homonym problem as an alternative to flushing on context switch.

但不是同义词问题.为此，您可以让OS确保每个VA的第12位=每个PA的第12位. 这称为页面着色.

But not the synonym problem. For that, you can have the OS ensure that bit 12 of every VA = bit 12 of every PA. This is called page coloring.

页面着色还可以解决同音异义问题，而无需硬件执行重叠的标记位，因为它给了1位，这与物理地址和虚拟地址相同. phys idx =虚拟idx. (但是，如果硬件要依赖于该不变式，则硬件将依赖于软件是正确的.)

Page coloring would also solve the homonym problem without the hardware doing overlapping tag bits, because it gives 1 more bit that's the same between physical and virtual address. phys idx = virt idx. (But then the HW would be relying on software to be correct, if it wanted to depend on this invariant.)

让标签与索引重叠的另一个原因是在收回期间回写:

外部高速缓存几乎始终是PIPT，并且内存本身显然需要物理地址.因此，在将其发送到内存层次结构中时，需要它的物理地址.

Outer caches are almost always PIPT, and memory itself obviously needs the physical address. So you need the physical address of a line when you send it out the memory hierarchy.

写回写缓存需要能够清除脏线(将脏线发送到L2或物理RAM)，这要在对存储进行TLB检查之后很长时间了.与负载不同，除非您将TLB结果存储在某个地方，否则它仍然没有浮动. VIPT的工作方式L1-> L2驱逐到PIPT转换工作

A write-back cache needs to be able to evict dirty lines (send them to L2 or to physical RAM) long after the TLB check for the store was done. Unlike a load, you don't still have the TLB result floating around unless you stored it somewhere. How does the VIPT to PIPT conversion work on L1->L2 eviction

让标签包含页面偏移量以上的所有物理地址位可以解决此问题:给定页面偏移量索引位和标签，您就可以构建完整的物理地址.

Having the tag include all the physical address bits above the page offset solves this problem: given the page-offset index bits and the tag, you can construct the full physical address.

(另一种解决方案是直写式高速缓存，因此即使无法从高速缓存标记+索引中重构数据，您也总是从TLB获取与数据一起发送的物理地址.或对于只读高速缓存(例如指令高速缓存)，没有回写；逐出=丢弃.)

(Another solution would be a write-through cache, so you do always have the physical address from the TLB to send with the data, even if it's not reconstructable from the cache tag+index. Or for read-only caches, e.g. instruction caches, there is no write-back; eviction = drop.)

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