彼得森的解决方案能否在现代CPU架构上正常工作? [英] Will Peterson's solution work correctly on modern CPU architectures?

问题描述

我正在从操作系统概念由Silberschatz，Galvin和Gagne撰写.

I am studying operating systems from Operating System Concepts by Silberschatz, Galvin, and Gagne.

在第229页上，这本书陈述了有关彼得森解决方案的信息:

On page 229, the book states this about Petersons Solution :

由于现代计算机体系结构执行基本计算机的方式 语言说明，例如加载和存储，没有任何保证 彼得森的解决方案将在这样的体系结构上正常工作.

Because of the way modern computer architectures perform basic machine language instructions, such as load and store, there are no guarantees that Peterson's solution will work correctly on such architectures.

我在 Wikipedia 上进行了查找，发现它似乎最接近一个解释:

I looked this up on Wikipedia and found this which appears to be the closest to an explanation :

大多数现代CPU对内存访问进行重新排序，以提高执行效率.这样的处理器通常通过存储器屏障指令来提供某种方式来强制在存储器访问流中进行排序.在对内存访问进行重新排序的处理器上实现Peterson算法和相关算法通常需要使用此类操作才能正常工作，以防止顺序操作以不正确的顺序发生.请注意，即使在不对指令进行重新排序的处理器上，也可能发生对内存访问的重新排序

Most modern CPUs reorder memory accesses to improve execution efficiency. Such processors invariably give some way to force ordering in a stream of memory accesses, typically through a memory barrier instruction. Implementation of Peterson's and related algorithms on processors which reorder memory accesses generally requires use of such operations to work correctly to keep sequential operations from happening in an incorrect order. Note that reordering of memory accesses can happen even on processors that don't reorder instructions

我很难理解这是什么意思，或者甚至是答案.

I am having trouble understanding what this means or if this is even the answer.

那么，为什么不能保证Peterson的解决方案可以在现代体系结构上工作?

So, why is Peterson's solution not guaranteed to work on modern architectures ?

推荐答案

在具有一个CPU的系统上，由于按照程序顺序观察了程序自身的行为，因此可以确保使用Peterson的算法.

On a system with one CPU, Peterson's algorithm is guaranteed to work, because program's own behavior is observed in program order.

在具有多个CPU的系统上，该算法可能无法正常工作，因为在一个CPU上发生的事件的程序顺序在另一个CPU上可能会有所不同.

On systems with multiple CPUs the algorithm may fail to work because the program order of events occurring on one CPU may be perceived differently on another.

这可能会导致及早进入关键部分(当它仍被另一个线程使用)和过早退出关键部分(当共享资源的工作尚未完成时).

That may cause early entering into the critical section (while it's still in use by another thread) and early exiting from the critical section (when the work with the shared resource hasn't been finished yet).

因此，需要确保在CPU内部看到的事件顺序在外部是相同的.内存屏障可以确保这种序列化.

For this reason one needs to ensure that the order of events occurring inside the CPU is seen the same outside. Memory barriers can ensure this serialization.

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