'<< Verilog中的'运算符 [英] ' << ' operator in verilog
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问题描述
我有一个verilog代码,其中的一行如下:
i have a verilog code in which there is a line as follows:
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
此处将存储在RAM_DEPTH
中的内容以及<<
运算符在此处的作用.
here what will be stored in RAM_DEPTH
and what does the <<
operator do here.
推荐答案
<<
是二进制移位,将1左移8位.
<<
is a binary shift, shifting 1 to the left 8 places.
4'b0001 << 1 => 4'b0010
>>
是将MSB加0的二进制右移.
>>>
是有符号移位,如果左输入是有符号的,则它将保持MSB的值.
>>
is a binary right shift adding 0's to the MSB.
>>>
is a signed shift which maintains the value of the MSB if the left input is signed.
4'sb1011 >> 1 => 0101
4'sb1011 >>> 1 => 1101
三种指示左操作数的方式:
Three ways to indicate left operand is signed:
module shift;
logic [3:0] test1 = 4'b1000;
logic signed [3:0] test2 = 4'b1000;
initial begin
$display("%b", $signed(test1) >>> 1 ); //Explicitly set as signed
$display("%b", test2 >>> 1 ); //Declared as signed type
$display("%b", 4'sb1000 >>> 1 ); //Signed constant
$finish;
end
endmodule
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