将两个inout绑在一起vhdl [英] tie two inout together vhdl

问题描述

我想通过FPGA驱动双向逻辑信号. PGD​​_ICD<-> PGD_TARGET 对于那些认识到Microchip ICD3的人来说，您知道PGD线是双向的. 我读过，我们不能做那样的事情，但是你有什么主意吗? 非常感谢

I want to drive a birectionnal logic signal through the FPGA. PGD_ICD <--> PGD_TARGET for those who have recognized the Microchip ICD3 you know that PGD line is bidirectional. I've read that we can't do something like that but have you any idea ? many thanks

推荐答案

在不知道总线协议的情况下将双向总线通过FPGA的情况.

Passing a bidirectional bus through an FPGA without knowing the bus protocol won't work.

尽管FPGA I/O引脚确实支持三态逻辑信号(浮动输出状态)，但是您将需要知道何时将值驱动到输出上以及何时将输出三态(高阻抗或"Z").

While FPGA I/O pins do support tristate logic signals (floating output state), you will need to know when to drive a value onto the output, and when to tristate the output (high impedence, or 'Z').

一旦要驱动一个值的信号(例如out_enable)为"1"，而输出为浮动状态的信号为"0"，则可以使用三态缓冲器驱动输出:

Once you have a signal (for example out_enable) that is '1' when you want to drive a value and '0' when the output should be floating, you can use a tri-state buffer to drive the output:

out_pin <= out_signal when(out_enable='1') else 'Z';

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