使用Ruby创建Verilog解析器 [英] Create a Verilog Parser with Ruby
问题描述
我想为大学项目创建一个用Ruby编写的Verilog解析器
I would like to create a Verilog parser written in Ruby for a university project
我知道有像Bison和Yacc这样的解析器生成器.
I know there are parser generators like Bison and Yacc.
有人可以给我一些入门方面的建议吗?
Could anyone give me some advice on how to get started?
推荐答案
我已经有一个用ruby编写的非常基本的verilog解析器(gem)，名为 verilog ，如果您可以考虑为此做出贡献，或者它可能会给您一个入门的思路.
I already have a very basic verilog parser (gem) written in ruby called verilog, if you could consider contributing to that instead, or it might give an idea of how to start.
我还有一个名为 rubyit 的gem，这是用于使用erb解析文件并生成文件的命令行实用程序文件的标准版本.可以用于可扩展的Verilog模板，类似于generate语句，但是提供了灵活的端口列表并可以检查生成的代码.
I also have a gem called rubyit, which is command line utility to parse files with erb and generate the standard version of the file. Which can be used for extendable verilog templates, similar to generate statements but gives a flexible port list and ability to check the generated code.
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