为什么会出现此Modelsim错误？ “信号分配语句中的歧义类型”。 [英] Why this Modelsim error? "Ambiguous types in signal assignment statement."

问题描述

我正在尝试使用ModelSim Microsemi 10.2c编译以下示例：

I am trying to compile the following example with ModelSim Microsemi 10.2c:

architecture example of assignment_to_an_aggregate is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin

    (my_vowel, my_consonant) <= (a, b);

end;

它给出以下错误：

** Error: assignment_to_aggregates.vhdl(40): (vcom-1349) Ambiguous types in signal assignment statement.

   Possible target types are:
        std.STANDARD.TIME_VECTOR
        std.STANDARD.REAL_VECTOR
        std.STANDARD.INTEGER_VECTOR
        std.STANDARD.BIT_VECTOR
        std.STANDARD.BOOLEAN_VECTOR
        std.STANDARD.STRING

** Error: assignment_to_aggregates.vhdl(57): VHDL Compiler exiting

任何人都可以解释这是行不通的吗？为何编译器会认为TIME_VECTOR，STRING等是此分配目标的合理类型？注意：即使目标集合中只有相同类型的信号，我也会遇到同样的错误。

Anyone could explain whit this doesn't work? And why would the compiler think that TIME_VECTOR, STRING, etc. are reasonable types for the target of this assignment? Note: I get the same error even when the target aggregate has only signals of a same type.

谢谢！

推荐答案

虽然我无法评论Modelsim的类型消息的特殊性，但问题是无法从上下文中识别右侧聚合的类型。

While I can't comment on Modelsim's peculiarities of type messages, the problem is the type of the right hand side aggregate can't be discerned from the context.

尝试：

entity assignment_to_an_aggregate is
end entity;
architecture example of assignment_to_an_aggregate is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);

    type vowel_consonant is 
        record 
            vowel: vowel_type;
            consonant: consonant_type; 
        end record;

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin

    (my_vowel, my_consonant) <= vowel_consonant'(a,b);

end;

您会注意到，左边的聚合类型取决于右边的表达式

And you'll note that the left hand side aggregate depends on the right hand side expression for it's type.

（类型声明不承担任何模拟或合成负担，也没有命名对象声明为记录类型）。

(And a type declaration bears no simulation nor synthesis overhead burden, and no where is there a named object declared as a record type).

好，所以，如果我理解正确，那么分配右侧出现的所有内容都需要具有明确定义的类型？还是换一种说法，每个聚合都必须具有定义的类型？ – 5分钟前VHDL Addict

Ok, so if I understand correctly, then everything that appears on the right hand side of an assignment needs to have a explicitly defined type? Or to put it another way, every aggregate must have a defined type? – VHDL Addict 5 mins ago

否。在这种情况下，信号分配的目标是总计：

No. In this case the target of a signal assignment is an aggregate:

IEEE Std 1076-1993，8.4 Signal Assignment statement（-2008，10.5 / 10.5.2.1）：

IEEE Std 1076-1993, 8.4 Signal assignment statement (-2008, 10.5/10.5.2.1):

如果信号分配语句的目标采用
聚合的形式，则聚合的类型必须是可确定的从
的上下文中，不包括聚合本身，但包括
事实，即聚合的类型必须是复合类型。

If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type.

除了右手边还有什么其他上下文？您不能在左侧将合计设为合格的表达式。信号分配的目标必须命名且表达式没有名称。

What else is there for context besides the right hand side? You can't make the aggregate on the left hand side a qualified expression. The target of a signal assignment must be named and the expression has no name.

您收到的Modelsim错误消息未指定它正在抱怨的分配语句的哪一侧大约还有一些其他工具可能会更有启发性：

The Modelsim error message you got didn't specify which side of the assignment statement it was complaining about while some other tool might be more enlightening:

assignment_to_aggregate.vhdl：23：19：波形类型未知，请使用类型限定符

assignment_to_aggregate.vhdl:23:19: type of waveform is unknown, use type qualifier

您曾经注意到错误消息是为那些没有需要它们吗？

You ever notice error messages are intended for someone who doesn't need them?

这篇关于为什么会出现此Modelsim错误？ “信号分配语句中的歧义类型”。的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！