VHDL-带反馈的相位累加器 [英] VHDL - Phase Accumulator with feedback

问题描述

我正在尝试使用具有以下特征的VHDL创建一个相位累加器。

I am trying to create a phase accumulator using VHDL that has the following characteristics.

输入：

• D（输入信号）


• RESET


• CE


• CLK

• D (Input signal)
• RESET
• CE
• CLK

输出：

• Q（输出信号-反馈）

源代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Phase_accu is
port (
    D       : in std_logic_vector(3 downto 0);
    CE      : in std_logic;
    CLK     : in std_logic;
    RESET   : in std_logic;
    Q       : out std_logic_vector(15 downto 0)
);
end Phase_accu;

architecture Behavioral of Phase_accu is
begin

process(D, CE, CLK, RESET)
    begin
        if RESET = '1' then
            Q <= "0000000000000000";
        elsif rising_edge(CLK) then
            if CE = '1' then
                Q <= ("000000000000" & D) + Q;
            end if;
        end if;
end process;

end Behavioral;

我在尝试将2个信号合并以进行反馈时出现错误。 p>

I get an error with the line trying to merge together the 2 signals for feedback...

Q <= ("000000000000" & D) + Q;

无法读取输出 Q。

推荐答案

在VHDL-2008之前的VHDL修订版中，您无法读取 out 的值。解决此问题的通常方法是拥有输出的内部副本，并在需要获取其值时使用该内部副本：

You can't read the value of an out in VHDL revisions prior to VHDL-2008. The usual way to get around this is to have an internal copy of your output, and use that internal copy when you need to get its value:

[...]
Q : out std_logic_vector(15 downto 0);
[...]
signal Q_reg : std_logic_vector(15 downto 0);

process(D, CE, CLK, RES)
    begin

        if RES = '1' then
            Q_reg <= "0000000000000000";
        elsif rising_edge(CLK) then
            if CE = '1' then
                Q_reg <= ("000000000000" & D) + Q_reg;
            end if;
        end if;
end process;

Q <= Q_reg;

这篇关于VHDL-带反馈的相位累加器的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！