访问层次结构之外的顶级资源 [英] Access top level resources outside of hierarchy

问题描述

有一种方法可以在Verilog中综合架构，以便深度嵌套的终结点可以访问某些顶级管脚（来自.ucf），而无需在层次结构的每个模块中明确路由这些管脚。

is there a way to synthesize an architecture in verilog such that a deeply nested endpoint can access some top level pins (from a .ucf) without expressly routing the pins through every module of the hierarchy.

在我的情况下，我有一个带有深度嵌套端点的PCIe块。
在端点处有一个地址解码器，需要从顶层的引脚提供一些信号信息。

In my case i have a PCIe block with a deeply nested endpoint. AT the endpoint there have an address decoder that needs to provide some signal information from pins at the top level.

我宁愿不修改每个中间模块携带必要的电线。

I'd rather not modify every intervening module to carry the necessary wires.

我的网络搜索感到沮丧，因为术语 net和 bus在verilog中已经具有替代含义。

my web searches are frustrated because the terms 'net' and 'bus' already have alternative meanings in verilog.

我尝试了特定的分层命名，例如
top.button和top.LED，但仅成功访问了可读的针脚，但没有访问可写的针脚，这使我想起了我在这里缺少一些基本知识。

I have tried specific hierarchical naming like (for example) top.button and top.LED but have only succeeded in getting access to readable pins, but not writeable pins, leading me to assume i'm missing something fundamental here.

更新
我可以模拟此
http://www.edaplayground.com/x/AAq

并合成（类似的构造）而没有错误（Xilinx XST）
，但是当它在实际硬件
中运行时，LED上没有输出，所以我想知道是否不支持向上名称引用用于synt

and synthesize (a similar construct) without error (Xilinx XST) but there is no output on the LED when it is run in real hardware so i'm wondering if upwards name reference is not supported for synthesis?

推荐答案

是的，使用某些工具可以实现并且可以综合。我知道的唯一机制是在函数中使用静态变量来创建连接，调用该函数一次以设置值，一次调用该值。

Yes, this is possible and synthesisable using some tools. The only mechanism I'm aware of is to use a static variable in a function to create the "connection", calling the function once to set the value and once to get the value.

有关此示例，请查看我在Github上的概念验证

For an example of this, check out my proof-of-concept on Github

使用函数内部的静态变量在模块之间进行通信的SystemVerilog概念验证。

SystemVerilog proof-of-concept for using static variables inside functions to communicate between modules.

这允许进行连接，而不必在层次结构中添加布线。可能的应用包括将信号提取到逻辑分析仪，写入全局资源（事件日志，统计信息，UART等）。

This allows connections to be made without having to add wiring through the hierarchy. Possible applications include pulling signals out to logic analyser, writing to global resources (event log, statistics, UART etc.)

在Quartus 13中，我还没有尝试使用YMMV等其他工具。

This synthesises correctly in Quartus 13, I haven't tried it with other tools so YMMV.

UPDATE ：Xilinx Vivado当前不支持，请参见此线程。

UPDATE: Not currently supported by Xilinx Vivado, see this thread for details.

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