访问内存时，是否在缓存命中的情况下设置页表访问/脏位? [英] When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation?

问题描述

据我所知，CPU的内存访问涉及CPU缓存和MMU. CPU将尝试在高速缓存中查找其目标，如果发生高速缓存未命中，CPU将转向MMU.在通过MMU访问期间，对应页表项的被访问/脏位将由硬件设置.

As far as I know, a memory access of CPU involves CPU cache and MMU. CPU will try to find its target in cache and if a cache miss happens, CPU will turn to MMU. During accessing by MMU, the accessed/dirty bit of correspondent page table entry will be set by hardware.

据我所知，除非存在缓存未命中，否则大多数CPU设计都不会触发MMU，而我的问题是，是否仍会在缓存命中时设置页表项的已访问/脏位?还是与架构有关?

However to the best of my knowledge, most CPU design won't trigger the MMU unless there's a cache miss, and here my problem is, will the accessed/dirty bit of page table entry still be set under a cache hit? Or it's architecture related?

推荐答案

我认为您可以假设这些位缓存在TLB中，并且如果与TLB中的值和内核进行的访问存在任何不一致，微码辅助将被采用，并且位将被更新.例如，如果A ¹ 或D位为零并且发生访问或存储，则将检测到此情况并设置适当的位.

I think you can assume these bits are cached in the TLB, and if there is any inconsistency with the values in the TLB and accesses done by the core, a microcode assist will be taken and the bits will be updated. For example, if the A¹ or D bits are zero and an access or store happens, this condition will be detected and the appropriate bits will be set.

您还可以假定TLB命中的快速路径无法进入内存，并查看缓存的TLB位是否与RAM中的PTE一致.此外，在x86上，硬件不会将对PTE的更改(缓存无效样式)推送到TLB.也就是说，TLB 不连贯.

You can also assume that the fast path for TLB hits can't go to memory and see if the cached TLB bits are consistent with the PTEs in RAM. Furthermore, on x86 changes to PTE are not pushed, cache-invalidation style, to TLBs by hardware; that is, the TLB is not coherent.

这意味着，如果这些位以某些方式不同步，则可能无法正确更新它们.例如，如果在TLB中将A(地址D)位置1，并且发生访问(地址存储)，则即使PTE中的A(地址D)位置实际上未被置位，也不会发生任何事情.对位进行更改的实体负责刷新TLB，以便将来正确更新位.

This implies that if the bits are out of sync in certain ways, they will probably not be updated correctly. E.g., if the A (resp. D) bit is set in the TLB, and an access (resp. store) occurs, nothing will happen, even if the A (resp. D) bit is actually unset in the PTE. The entity making changes to the bits is responsible for flushing TLBs so that the bits are correctly updated in the future.

¹ 具有带有A == 0的TLB条目是很奇怪的:您希望该条目是由于访问而存在的，因此从头开始将A位置1.也许在某些情况下可能会发生这种情况，例如推测性访问或预取所带来的页面.

¹ Having a TLB entry with A == 0 is weird: you'd expect the entry to be there as a result of an access, so having the A bit set from the start. Perhaps there are some scenarios where this might occur, such as a page brought in by a speculative access or prefetch.

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