Verilog中的案例陈述 [英] Case statement in verilog

问题描述

我遇到了优先级编码器设计，并找到了一种使用case语句的新方法. 唯一令人困惑的是，案例声明是否优先考虑案例? 示例:

I came across priority encoder design and found out a new way to do it using a case statement. The only thing that is confusing is, does a case statement give priority to cases? Example:

case(1'b1)                                
  A[3]: Y<=4'b1000;             
  A[2]: Y<=4'b0100;  
  A[1]: Y<=4'b0010;  
  A[0]: Y<=4'b0001;  
  default:Y<=4'b0000;
endcase

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在这里，如果我给A作为1111 Y得到1000，即它赋予第一个case语句优先级. 为什么会这样?

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Here if I give A as 1111 Y gets 1000 i.e it gives priority to the first case statement. Why is this so?

推荐答案

是的，根据订单的顺序，有一个优先级.根据Verilog-2001规范的第9.5节:

Yes, there is a priority, based off of the order. According to the Verilog-2001 spec, section 9.5:

案例项表达式应按照给出的确切顺序进行评估和比较.在线性搜索期间，如果case项表达式之一与括号中给出的case表达式匹配，则应执行与该case项关联的语句.

The case item expressions shall be evaluated and compared in the exact order in which they are given. During the linear search, if one of the case item expressions matches the case expression given in parentheses, then the statement associated with that case item shall be executed.

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