如果我使用了异步复位该怎么办，我是否必须将其设置为同步复位? [英] What if I used Asynchronous reset, Should I have to make as synchronous turned it?

问题描述

在制造IC时(我指的是硬件中的物理设计). 据我所知，输入复位始终是异步的.我想知道如果我使用异步复位怎么办，我是否必须将其设置为同步?或我们可以只使用异步重置吗?

At we make IC( I mean physical design in Hardware). As i know, the input reset is always Asynchronous. I wonder that What if I used Asynchronous reset, Should I have to make into synchronous? or Can we just used asynchronous reset?

推荐答案

实际上，如果您的触发器具有时钟并且异步重置，则可以随时开始异步重置，但是您应该同步结束它.原因很简单:想象一下真正的异步.复位与时钟沿同时结束.您可以在这里轻松获得亚稳态，或者，例如，一半的触发器将接受时钟沿，而另一半的触发器仍将处于复位状态并错过相同的时钟沿，从而可能破坏您的设计.

In fact, if you have flip-flops, which are clocked AND asynchronously resetted, you can start reset asynchronously at any time, but you should end it synchronously. The reason for this is simple: imagine that truly async. reset ends simultaneously with the clock edge. You can easily get metastables here, or, for example, half of your flipflops would accept clock edge, while other half would be still in reset and miss the same clock edge, thus potentially ruining your design.

因此，基本上，您需要像这样同步外部异步重置:

So basically you need to synchronize external asynchronous reset like this:

module rst_resync
(
    input  wire clk,
    input  wire ext_rst_n,
    output wire rst_n
);

    reg [1:0] rst_resync;

    always @(posedge clk, negedge ext_rst_n)
    if( !ext_rst_n )
        rst_resync[1:0] <= 2'b00;
    else
        rst_resync[1:0] <= { rst_resync[0], 1'b1 };

    assign rst_n = rst_resync[1];

endmodule

这样，即使在没有时钟的情况下，您仍然可以随时重置设计(就像任何异步重置一样)，但是内部重置将与时钟同步结束.

This way, you are still able to reset your design at any time, and even in the absense of clock (as any async reset does), but internal reset will end synchronously to the clock.

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