“警告C0007:架构具有未绑定的实例".问题！ [英] "Warning C0007 : Architecture has unbound instances" issue!

问题描述

我从《数字设计基础》一书附带的CD中获得以下源代码.

I have the following source code from the CD attached with "Fundamental of Digital Design" book.

当我尝试运行该程序时，它给了我以下错误:

When I tried run the program, it gave me the following error:

Compiling Fig17_13.vhd...
C:\Users\SPIDER\Desktop\EE460\The Final Project\Fig17_13.vhd(25): Warning C0007 : Architecture has unbound instances (ex. ct2)
Done

如何解决此问题?

这是代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity c74163test is
    port(ClrN,LdN,P,T1,Clk: in std_logic;
       Din1, Din2: in std_logic_vector(3 downto 0);
       Count: out integer range 0 to 255;
       Carry2: out std_logic);
end c74163test;

architecture tester of c74163test is
    component c74163
       port(LdN, ClrN, P, T, Clk : in std_logic;  
         D: in std_logic_vector(3 downto 0);
       Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
    end component;
    signal Carry1: std_logic;
    signal Qout1, Qout2: std_logic_vector(3 downto 0);
begin
    ct1: c74163 port map (LdN,ClrN,P,T1,Clk,Din1,Carry1, Qout1);
    ct2: c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,Carry2,Qout2);
    Count <= Conv_integer(Qout2 & Qout1);
end tester;

推荐答案

您之前确实读过实例化的设计吗(我想它在Fig17_12.vhd中)?否则，您的实例只是一个黑匣子(我想这就是未绑定实例"的意思).

Did you actually read the instantiated design before (I guess it's in Fig17_12.vhd)? Otherwise your instance is just a blackbox (what I guess is meant by "unbound instance").

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