"And"的条件执行在ARM语法中 [英] Conditional Execution for "And" in ARM syntax

问题描述

我试图掌握ARM编程中的条件执行.

I'm trying to get a grip on conditional execution within ARM programming.

所以我有点理解这样的情况:

So I kind of understand a situation like this:

if ( (R0 != 5) || (R2 != R3) ) ; != means not equal,  || mean OR 
{  
R4-- ; // R4 = R4 - 1 
}

而ARM版本是:

CMP   R0, 5
CMPEQ R2, R3
SUBNE R4, R4, 1

我很好奇ARM如何知道这是一个或"(||).因此，它做了两次比较.但是，如果两个比较都不正确，将会发生什么.那是NE吗?如果它们不同，会发生什么(如下面的示例).

I was curious how ARM knows that that is an "OR" (||). So it does two compares. But what happens if both compares aren't correct. Is that what NE does? What happens if they were different (like example below).

所以可以说代码是这样的:

So lets say the code is this:

if ( (R0 > 5) && (R2 != R3) ) ; != means not equal,  && mean AND 
{  
R4-- ; // R4 = R4 - 1 
}

您将如何使用ARM中的条件指令编写此代码?

How would you write this with conditional instructions in ARM?

谢谢！

推荐答案

这是一些简单的逻辑，对于'OR'情况似乎很直观.我认为"AND"更为简单.关键是只有在第一个条件为"AND"传递时，才应评估第二个条件.对于或"情况，情况恰恰相反.您可以将逻辑电路短路，而不必费心执行第二个条件.

This is some simple logic that seems counter intuitive for the 'OR' case. The 'AND' is simpler in my opinion. The key is that the 2nd condition should only be evaluated if the first passed for 'AND'. For the 'OR' case it is the opposite. You short circuit the logic and don't bother to execute the 2nd condition.

以下是与"案的步骤，

1. 测试cc1
2. 如果cc1测试cc2
3. 如果是cc2，则执行

如果'cc1 == cc2'并且第一个为false，则不会执行步骤2，因此也不执行第3步.

If 'cc1 == cc2' and the first is false then step 2 doesn't execute and hence not 3 as well.

以您为例，

if((R0 > 5) && (R2 != R3)) R4--; 

它将翻译为

TST   R2, R3     ; step 1 as (R2 != R3)
MSREQ CPSR_f,#3<<30 ; set N and Z flags  (also APSR_nz)
CMPNE R0, #5     ; step 2 as (R0 > 5)
SUBPL R4, #1     ; step 3

必须注意确保第1步中的第一个测试不会影响第3步的执行.可以对测试的"AND"条件重新排序，因为必须同时测试这两个条件.

Care must be taken to ensure that the first test in step 1 does not influence the execution of step 3. Tests can be re-ordered for the 'AND' condition as both must be tested.

请参阅:
在条件执行中留出空间
状态注册上的HeyRick

See:
Dave space on conditional execution
HeyRick on status register

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