内存屏障是CPU执行的指令，还是仅仅是标记? [英] Is a memory barrier an instruction that the CPU executes, or is it just a marker?

问题描述

我试图确切地了解什么是内存障碍. 根据目前为止我所知道的，使用内存屏障(例如:mfence)来防止从内存屏障之前到之后以及之后到内存之前重新排序指令.

I am trying to understand what is a memory barrier exactly. Based on what I know so far, a memory barrier (for example: mfence) is used to prevent the re-ordering of instructions from before to after and from after to before the memory barrier.

这是一个正在使用的内存屏障的示例:

This is an example of a memory barrier in use:

instruction 1
instruction 2
instruction 3
mfence
instruction 4
instruction 5
instruction 6

现在我的问题是:mfence指令只是一个标记，告诉CPU以什么顺序执行指令?还是CPU实际执行的一条指令，就像它执行其他指令一样(例如:mov).

Now my question is: Is the mfence instruction just a marker telling the CPU in what order to execute the instructions? Or is it an instruction that the CPU actually executes like it executes other instructions (for example: mov).

推荐答案

CPU在其代码中遇到的每个字节序列都是CPU执行的一条指令.没有其他种类的说明.

Every byte sequence that the CPU encounters amongst its code is an instruction that the CPU executes. There are no other kinds of instructions.

您可以在增强功能.

You can see this clearly in both the Intel instruction set reference and the specific page for mfence.

MFENCE
对所有内存加载执行序列化操作 以及之前发布的存储到内存的指令 MFENCE指令.此序列化操作可确保前面的每个加载和存储指令 程序顺序中的MFENCE指令在随后的任何加载或存储指令之前变为全局可见 MFENCE指令.

MFENCE
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows the MFENCE instruction.

MFENCE指令针对所有加载和存储指令进行排序，其他 MFENCE指令，任何LFENCE和SFENCE指令以及任何序列化指令(例如CPUID) 操作说明). MFENCE不会序列化指令流. 弱排序的内存类型可通过以下技术来实现更高的处理器性能: 乱序问题，推测性读取，写入合并， 和写折叠.消费者的程度 数据识别或知道数据是弱排序的，在不同的应用程序中会有所不同，并且可能对应用程序未知 此数据的生产者. MFENCE指令提供 一种确保加载和存储的高效性能方式 产生弱顺序的例程之间的顺序 ed结果和使用该数据的例程.

The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID instruction). MFENCE does not serialize the instruction stream. Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store ordering between routines that produce weakly-order ed results and routines that consume that data.

处理器可以自由地推测性地获取和缓存数据 来自使用WB，WC和 WT内存类型.这种推测性获取可以随时发生，并且与指令执行无关.因此，它 关于MFENCE的执行没有命令 操作说明;可以在执行MFENCE指令之前，之中或之后将数据推测性地带入高速缓存.

Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it is not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches speculatively just before, during, or after the execution of an MFENCE instruction.

从摘录中可以看到，MFence指令做了很多工作，而不仅仅是做某种标记.

As you can see from the excerpt the MFence instruction does quite a bit of work, rather than just being a marker of some sort.

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