英特尔和AMD x86-64实现的兼容子集是什么? [英] What is the compatible subset of Intel's and AMD's x86-64 implementations?
问题描述
在学习x86-64组装时，我遇到了"x86-64"的Intel 64和AMD64实现之间的第一个不兼容性:解决方案
历史记录:英特尔在Itanium中实现了其64位ISA，他们将其称为IA-64，它完全替代了32位x86 ISA.处理器行. IA-64并未与x86向后兼容，也从未真正在高端服务器市场之外流行.
AMD创建了AMD64 ISA，它是对x86 ISA的逐步发展. AMD64迅速得到普及和接受，英特尔也采用了它，但在不同时期将其称为IA-32e，EM64T和Intel64. Intel64和AMD64几乎相同，但有一些区别.
维基百科列出了这些区别:
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当源为零且操作数大小为32位时，Intel 64的BSF和BSR指令的行为与AMD64的行为不同.处理器将零标志设置为零，而未定义目标的高32位.
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AMD64需要不同的微代码更新格式并控制MSR(特定于模型的寄存器)，而Intel 64则实现了仅使用其32位处理器的微代码更新.
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Intel 64缺少一些在AMD64中被视为体系结构的MSR.这些包括SYSCFG，TOP_MEM和TOP_MEM2.
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Intel 64仅在64位模式下(不允许在兼容模式下)允许SYSCALL/SYSRET，并且在两种模式下都允许SYSENTER/SYSEXIT.在长模式的两个子模式下，AMD64都缺少SYSENTER/SYSEXIT.
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在64位模式下，前缀为66H(操作数大小覆盖)的附近分支的行为不同. Intel 64会忽略此前缀:指令具有32位符号扩展偏移量，并且指令指针不会被截断. AMD64在指令中使用16位偏移量字段，并清除指令指针的前48位.
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AMD处理器在执行80位信令NaN的FLD或FSTP时会引发浮点无效异常，而Intel处理器则不会.
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Intel 64缺乏保存和恢复浮点状态的简化(因此更快)版本(涉及FXSAVE和FXRSTOR指令)的能力.
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最近的AMD64处理器通过长模式分段限制启用(LMSLE)位重新引入了对分段的有限支持，以简化64位客户机的虚拟化.
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使用SYSRET返回非规范地址时，AMD64处理器以特权级别3执行常规保护故障处理程序，而在Intel 64处理器上则以特权级别0执行.
While learning x86-64 assembly, I came across my first incompatibility between Intel 64 and AMD64 implementations of "x86-64": Why does syscall compile in NASM 32 bit output while popa does not compile in 64 bit? syscall is valid in the compatibility mode of one but not the other.
Is there a better way of finding out those incompatibilities besides carefully reading both manuals and comparing them, which is error prone and duplicates my manual reading effort when aiming for portability?
For example, it would be much easier if there was either:
- a standard subset which both Intel and AMD claim to follow
- comments on the Intel manual about AMD compatibility since AMD was the one to invent x86-64. But of course, this would be hard for Intel to maintain, and the Intel manuals don't contain the word AMD.
- some general official or non-official guideline which assures compatibility of certain parts. For example, something like: compatibility mode may be incompatible, but 64-bit mode not.
- some well maintained list of incompatibilities by Intel, AMD or some third party
History note: Intel implemented their 64-bit ISA, which they called IA-64 which was a complete replacement of the 32-bit x86 ISA, in their Itanium line of processors. IA-64 wasn't backward compatible with x86 and never really became popular outside the high-end server market.
AMD created the AMD64 ISA as an incremental evolution over the x86 ISA. AMD64 gained popularity and acceptance quickly and Intel adopted it as well, but called it IA-32e, EM64T and Intel64 at various times. Intel64 and AMD64 are nearly identical with a few differences.
Wikipedia lists these differences:
Intel 64's BSF and BSR instructions act differently than AMD64's when the source is zero and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.
AMD64 requires a different microcode update format and control MSRs (model-specific registers) while Intel 64 implements microcode update unchanged from their 32-bit only processors.
Intel 64 lacks some MSRs that are considered architectural in AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.
Intel 64 allows SYSCALL/SYSRET only in 64-bit mode (not in compatibility mode), and allows SYSENTER/SYSEXIT in both modes. AMD64 lacks SYSENTER/SYSEXIT in both sub-modes of long mode.
In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel 64 ignores this prefix: the instruction has 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses 16-bit offset field in the instruction, and clears the top 48 bits of instruction pointer.
AMD processors raise a floating point Invalid Exception when performing an FLD or FSTP of an 80-bit signalling NaN, while Intel processors do not.
Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).
Recent AMD64 processors have reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease virtualization of 64-bit guests.
When returning to a non-canonical address using SYSRET, AMD64 processors execute the general protection fault handler in privilege level 3, while on Intel 64 processors it is executed in privilege level 0.
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