在8086中从RAM加载程序 [英] Loading program from RAM in 8086

问题描述

8086正在使用16位指令，但RAM地址仅保留8位，那么CPU如何从RAM加载程序呢?它是否加载一个地址，然后检查指令是否需要1/2/3字节(例如，将立即数移动到寄存器8/16位)，然后执行该操作，或者我弄错一个RAM的空间"为16位大吗?

The 8086 is using 16-bit instruction but the RAM addresses only hold 8-bit how does the CPU load programms from the RAM then ? Does it load one address and then checks if the instruction needs 1/2/3 bytes (e.g. moving a immediate to a register 8/16 bit) and then executes the operation or am I getting it wrong that one RAM 'space' is 16-bit big ?

推荐答案

许多指令都是多字节的，是的，这意味着它们跨越两个或多个地址.

Many instructions are multi-byte, and yes that means they span two or more addresses.

8086的IIRC内存总线是16位的，因此它可以在一次操作中加载16位(两个相邻地址).您将字节可寻址内存与总线宽度混淆了.

IIRC, 8086's memory bus is 16-bit, so it can load 16 bits (two adjacent addresses) in a single operation. You're confusing byte-addressable memory with the bus width.

是否加载一个地址然后检查指令是否需要1/2/3字节(例如将立即数移到8/16位寄存器)

Does it load one address and then checks if the instruction needs 1/2/3 bytes (e.g. moving a immediate to a register 8/16 bit)

它不断地将指令字节提取到6字节的缓冲区中(一次2字节，因为它是具有16位总线的16位CPU).缓冲区足够大，可以容纳最大允许的8086指令(不包括前缀，IDK可能会单独解码).完成上一条指令后，它会查看缓冲区.请参阅下面的链接以获得更好的描述，但是它可能会尝试将缓冲区解码为一条完整的指令.如果它在找到指令的末尾之前到达了提取缓冲区的末尾，它将一直等到下一个提取周期完成并再次尝试.

It continually fetches instruction bytes into a 6-byte buffer (2 bytes at a time, because it's a 16-bit CPU with 16-bit busses). The buffer is large enough to hold the largest allowed 8086 instruction (excluding prefixes, which might be decoded separately, IDK). When it's done executing the previous instruction, it looks at the buffer. See the link below for a better description, but it probably tries to decode the buffer as a whole instruction. If it hits the end of the fetch buffer before finding the end of the instruction, it waits until the next fetch cycle has completed and tries again.

另请参见: 8086 CPU体系结构 ，这是"8086代码提取"的首个热门产品.它确认获取和执行确实重叠，因此以最基本的方式进行了流水线操作.

See also: 8086 CPU architecture, which was the first hit for "8086 code fetch". It confirms that fetch and execute do overlap, so it's pipelined in the most basic way.

TL:DR:它将提取到缓冲区中，直到它具有完整的要解码的指令为止.然后，它将多余的字节移到缓冲区的前面，因为它们是下一条指令的一部分.

TL:DR: It fetches into a buffer until it has a whole instruction to decode. Then it shifts any extra bytes to the front of the buffer, because they're part of the next instruction.

我已经读到，通常指令获取是8086的瓶颈，因此针对代码大小的优化远远超过了其他所有功能.

I've read that usually instruction-fetch is the bottleneck for 8086, so optimizing for code-size outweighed pretty much everything else.

流水线化的CPU不必等待上一条指令的执行完成就可以开始解码.现代CPU还具有很多更高带宽的代码提取功能，因此它们准备有待执行的已解码指令队列(分支将其弄乱时除外).请参见 x86 标签Wiki.

A pipelined CPU wouldn't have to wait for execution of the previous instruction to finish to get started on decoding. Modern CPUs also have much higher bandwidth code-fetch, so they have a queue of decoded instructions ready to go (except when branches mess this up.) See http://agner.org/optimize/, and other links in the x86 tag wiki.

另外，一些非常常见的指令是单个字节，例如 push r16 .

Also, some very common instructions are a single byte, like push r16.

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