在Verilog设计中产生时钟故障 [英] Producing a clock glitch in a Verilog design

问题描述

我正在使用Verilog设计芯片。我有一个3位计数器。我希望当计数器处于第8个循环时，应该出现时钟故障，然后才能正常工作。在Verilog设计中产生时钟毛刺的可能方法是什么？

I am designing a chip using Verilog. I have a 3-bit counter. I want that when the counter is in its 8th loop, there should be a clock glitch, and thereafter work normally. What could be the possible ways of producing a clock glitch in a Verilog design?

推荐答案

在时钟信号上注入毛刺的一种方法是使用测试台上的 force 和 release ：

One way to inject glitches on a clock signal is to use force and release from your testbench:

module tb;

reg clk;
reg [2:0] cnt;
reg reset;

always begin
    #5 clk <= 0;
    #5 clk <= 1;
end

always @(posedge clk or posedge reset) begin
    if (reset) begin
        cnt <= 0;
    end else begin
        cnt <= cnt + 1;
    end
end

always begin: inject_clk_glitch
    wait(cnt == 7);
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
end

initial begin
    reset = 1;
    #20 reset = 0;
    #500 $finish;
end

endmodule

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