在实模式下运行时，现代x86处理器上是否可以使用流水线/ OoOE？ [英] Is pipelining/OoOE available on modern x86 processors when running in real mode?
问题描述
在现代x86处理器上运行引导加载程序时，处理器将以实地址模式运行。
When running a boot-loader program on a modern-day x86 processor, the processor will be running in real-address mode. Will its instruction pipelining features be active in real mode, or not?
推荐答案
是，乱序无论采用哪种模式，现代微体系结构的核心都基本相同。大部分差异在于解码器。请参见 Agner Fog的microarch pdf 和 x86 标签Wiki，以了解现代CPU实际上如何在内部工作。
Yes, the out-of-order core in modern microarchitectures operates basically the same regardless of mode. Most of the difference is in the decoders. See Agner Fog's microarch pdf and other links in the x86 tag wiki for details of how modern CPUs actually do work internally.
由于它与禁用分页的32位模式非常相似，但默认地址大小和操作数大小不同，因此可能需要额外的硅才能在16位模式下表现出不同。
It would probably take extra silicon to behave differently in 16bit mode, since it's very similar to 32bit mode with paging disabled, but with a different default address-size and operand-size.
I已经读到，当段的基数为非零时，AMD CPU的速度会稍微慢一些。 （或者我猜是在16位模式下：当段寄存器本身设置为非零值时，因为在16位模式下它们被直接使用，而不是用作描述符的选择器。）
I've read that AMD CPUs are slightly slower when segments have a non-zero base. (Or I guess in 16bit mode: when segment registers themselves are set to non-zero values, since in 16bit mode they're used directly, rather than being selectors for descriptors.)
Keep in mind that many common 16bit idioms like loop are terrible.
此外，部分寄存器的运行速度很容易干扰如果您不小心，则会乱序执行。 Intel P6系列和SnB系列CPU分别重命名了部分寄存器，因此写入AX不会对EAX / RAX的全部内容有错误的依赖性。稍后在SnB之前的CPU上合并时可能会出现停顿，或者在Haswell之前的SnB上只会出现较小的减速。
Also, partial-register slowdowns can easily interfere with out-of-order execution if you aren't careful. Intel P6-family and SnB-family CPUs rename partial registers separately, so writing to AX doesn't have a false dependency on the full contents of EAX/RAX. There can be stalls when merging later on CPUs before SnB, or just minor slowdowns on SnB before Haswell.
所有其他微体系结构都将 mov ax，5 作为 eax 的读-修改-写，因此它不会破坏对 ax 。如果您不小心，这对于无序执行可能是一个巨大的问题。
All other microarchitectures treat mov ax, 5 as a read-modify-write of eax, so it doesn't break the dependency chain on the old value of ax. This can be a huge problem for out-of-order execution if you aren't careful.
阅读Agner Fog的手册以了解更多信息。
Read Agner Fog's manuals to learn more.
我忘记了16位寻址模式可能无法正常运行。 32位代码不需要它们很快，而64位代码根本不能使用16位地址。 （64位代码中的地址大小前缀表示地址大小= 32位。）
16bit addressing modes might not perform well, I forget. 32bit code doesn't need them to be fast, and 64bit code can't use 16bit addresses at all. (The address-size prefix in 64bit code means address-size = 32bits.)
VEX编码指令（包括BMI2整数指令像 pext 一样，在实模式下不可用。 此英特尔论坛主题暗示可能是由于现有软件（NTVDM）使用机器代码作为保护模式的陷阱。 （即VEX使用的LDS / LES非法操作数相同）。因此，使VEX编码的指令仍然生成 #UD 对于向后兼容性很重要。
VEX-coded instructions (including BMI2 integer instructions like pext) aren't available in real mode. This Intel forum topic suggests that may be due to existing software (NTVDM) using the machine code as a trap to protected mode. (i.e. the same illegal operands to LDS/LES that VEX uses). Making VEX-coded instructions still generate #UD is thus important for backwards compatibility.
SSE仍在实模式下可用， 如果您使用正确的CR设置启用它。
SSE is still available in real mode, though, if you enable it with the right CR setting.
（VEX / EVEX 可在16位受保护的模式下使用，但不能在真实或虚拟8086模式下使用。< a href = https://stackoverflow.com/questions/44089163/is-x86-32-bit-assembly-code-valid-x86-64-bit-assembly-code> x86 32位汇编代码是否有效x86 64位汇编代码？）
(VEX/EVEX are available in 16-bit protected mode, but not real or virtual-8086 mode. Is x86 32-bit assembly code valid x86 64-bit assembly code?)
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