什么是增加延迟的正确方法？ 74HCT151，verilog模型对数据表是否准确？ [英] What is the proper way to add delays to, eg. 74HCT151, verilog model so it is accurate to the datasheet?
问题描述
向这种74hct151模型添加延迟的正确方法是什么-参见下文。
另请参阅我在解决方案上的工作。
我希望看到一个7400计时的完全准确（尽可能）的Verilog模型，以便我能理解问题并建立自己的解决方案。拥有。 74151之所以有趣，是因为Y和_Y路径的时间不同，也因为它是我自制的 TTL路径所需要的最新路径。 cpu。
我正在使用Icarus，因此我需要一个解决方案。我没有其他工具，而且我知道有些工具具有错误/怪癖/缺少功能，因此某些可以在商业工具上使用但不能在Icarus上使用的东西是一个问题。
我希望有人会给我看一个解决方案，以便我学习。
我在下面有一个解决方案，但我认为这可能有点麻烦。
我想要一个设计可以解决现实中的小故障。但是由于我的延误操作，我之前的尝试抑制了小故障。我相信这被称为传输延迟。
如以下文档中所述，使用运输延迟对于发现故障风险很有用。.4.3节
https://www.google.co.uk/url?sa=t&source=web&rct=j&url=http://cs.baylor。 edu /〜maurer / aida / desauto / chapter4.pdf& ved = 2ahUKEwjYtpS06pHsAhUEXRUIHVtJAos4FBAWMAB6BAgAEAE& usg = AOvVaw1CUNhobqxQe-pQIEZiBKm _p
数据表说，这种芯片在过渡期间会出现毛刺，这是我在最佳时机拍摄的
这些所需的延迟来自数据表fo r HCT单位为ns
I至Y = 19
I至_Y = 19
S至Y = 20
S至_Y = 20
_E至Y = 16
_E到_Y = 18
过渡时间Y，_Y = 7
另请参见 https://assets.nexperia.com/documents/data-sheet/74HC_HCT151_Q100.pdf
下面的基本代码没有延迟。
如何正确实现？
请参阅edaplayground
我希望有一种更惯用的方式来获取这些时间。
这是没有延迟的基本逻辑。 ...
`timescale 1ns / 1ns
module hct74151（_E，I，S，Y ，_Y）;
输出Y，_Y;
输入[2：0] S;
输入[7：0] I;
输入_E;
导线o =
（S == 0& I [0]）||
（S == 1& I [1]）||
（S == 2& I [2]）||
（S == 3& I [3]）||
（S == 4& I [4]）||
（S == 5& I [5]）||
（S == 6& I [6]）||
（S == 7& I [7]）;
分配Y = _E == 0？ o：0； 0：0。
指定_Y =！Y;
总是@ *开始
$ display（％9t％m，$ time，``_E =％1b I =％8b S =％1d Y =％b _Y =％b"，_ E，I，S，Y，_Y）；
结束
结束模块
：
这是我的解决方案，但这是惯用法吗？
在 icarus 上还有更好的方法吗？
模块hct74151（_E，I，S，Y，_Y）;
参数LOG = 0;
输出Y，_Y;
输入[2：0] S;
输入[7：0] I;
输入_E;
//设置时序将根据数据PD延迟信号，然后在最后一刻将它们组合起来。
逻辑[7：0] ID；
逻辑[2：0] Sd；
总是@ *
Id< =＃（19）I;
总是@ *
Sd< =＃（20）S;
//根据nexperia _E-> _Y慢于_E-> Y
逻辑_Ed，Ed;
总是@ *
_Ed< =＃（13）_E;
总是@ *
Ed< =＃（18）！ _E;
//组合
导线O =
（Sd == 0& ID [0]）||
（Sd == 1& Id [1]）||
（Sd == 2& Id [2]）||
（Sd == 3& Id [3]）||
（Sd == 4&Id [4]）||
（Sd == 5&Id [5]）||
（Sd == 6&Id [6]）||
（Sd == 7&Id [7]）;
分配Y = _Ed == 0？ O：0； 0：0。
指定_Y = Ed == 1吗？ ！O：1;
如果（LOG）总是@ *
开始
$ display（％9t％m，$ time， _E =％1b I =％8b S =％1d Y =％b _Y =％b（_Ed =％b，Ed =％b），_ E，I，S，Y，_Y，_Ed，Ed）；
结束
结束模块
What is the proper way to add delays to this model of a 74hct151 - see below. See also my effort at a solution.
I would like to see even one fully accurate (as possible) verilog model of 7400 timings so I could understand the concerns and build my own. The 74151 is interesting because the Y and _Y paths have different times and also because it's the most recent one I've needed for my homebrew"TTL" cpu.
I am using Icarus so I need a solution for that. I don't have other tools and I know that some tools have bugs/quirks/missing features so something that works on a commercial tool but not Icarus is an issue.
I am hoping someone would show me a solution so I can learn.
I do have a solution below but I think it's probably bit pants.
I want a design that allows through realistic glitches.but my earlier attempts suppressed short glitches due to how I was doing delays. I believe this is called "transport delay" as opposed to "inertial delay".
As mentioned in the following document using transport delays is useful for finding glitch risks.. section 4.3 https://www.google.co.uk/url?sa=t&source=web&rct=j&url=http://cs.baylor.edu/~maurer/aida/desauto/chapter4.pdf&ved=2ahUKEwjYtpS06pHsAhUEXRUIHVtJAos4FBAWMAB6BAgAEAE&usg=AOvVaw1CUNhobqxQe-pQIEZiBKm_
With correct delays I am expecting to see a transition glitch on the Y/_Y during certain transitions due to the difference in the S and I propagation delay.
The data sheet says this chips glitches during transitions and this shows up in my best shot at the timings
These needed delays are taken from datasheet for HCT in ns
I to Y = 19
I to _Y = 19
S to Y = 20
S to _Y = 20
_E to Y = 16
_E to _Y = 18
transition time Y, _Y = 7
See also https://assets.nexperia.com/documents/data-sheet/74HC_HCT151_Q100.pdf
The basic code below has no delays.
How do I implement correctly?
See edaplayground link above for my novice solution.
I expect there is a more idiomatic way to get these timings.
Here is the basic logic without delays....
`timescale 1ns/1ns
module hct74151(_E, I, S, Y, _Y);
output Y, _Y;
input [2:0] S;
input [7:0] I;
input _E;
wire o =
(S==0 & I[0]) ||
(S==1 & I[1]) ||
(S==2 & I[2]) ||
(S==3 & I[3]) ||
(S==4 & I[4]) ||
(S==5 & I[5]) ||
(S==6 & I[6]) ||
(S==7 & I[7]);
assign Y = _E==0 ? o : 0;
assign _Y = !Y;
always @* begin
$display("%9t %m ", $time, "_E=%1b I=%8b S=%1d Y=%b _Y=%b ", _E, I, S, Y, _Y);
end
endmodule
:
Here is my solution, but is it idiomatic? Is there a better way that works on icarus?
module hct74151(_E, I, S, Y, _Y);
parameter LOG=0;
output Y, _Y;
input [2:0] S;
input [7:0] I;
input _E;
// setup timing be delaying the signals according to the data PD then combine them at last minute
logic [7:0] Id;
logic [2:0] Sd;
always @*
Id <= #(19) I;
always @*
Sd <= #(20) S;
// according to nexperia _E->_Y is slower than _E->Y
logic _Ed, Ed;
always @*
_Ed <= #(13) _E;
always @*
Ed <= #(18) ! _E;
// combine
wire O =
(Sd==0 & Id[0]) ||
(Sd==1 & Id[1]) ||
(Sd==2 & Id[2]) ||
(Sd==3 & Id[3]) ||
(Sd==4 & Id[4]) ||
(Sd==5 & Id[5]) ||
(Sd==6 & Id[6]) ||
(Sd==7 & Id[7]);
assign Y = _Ed==0 ? O : 0;
assign _Y = Ed==1 ? !O : 1;
if (LOG) always @*
begin
$display("%9t %m ", $time, "_E=%1b I=%8b S=%1d Y=%b _Y=%b (_Ed=%b, Ed=%b)", _E, I, S, Y, _Y, _Ed, Ed);
end
endmodule
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