在vhdl中计算（并验证）以太网FCS（crc32） [英] calculate (and validate) ethernet FCS (crc32) in vhdl
问题描述
我正在使用 Spartan 3E入门套件，我正在尝试通过100MBit链接在其上接收以太网帧。
I'm using the Spartan 3E Starter Kit and I'm trying to receive Ethernet frames on it via a 100 MBit link.
对于那些不知道的人，该板配备了PHY芯片，可以暴露出25MHz的接收时钟。我已经（相当多地）通过缓冲接收的帧并通过串行链接重新发送来验证接收工作是否正常。
For those who don't know, the board features a PHY chip, exposing the receiving clock with 25 MHz. I have (pretty much) verified that receiving works fine by buffering the received frames and resending them via a serial link.
此外，我使用的是 outputlogic.com的CRC32生成器。我将接收到的半字节聚合为字节，然后将其转发给CRC。在帧的最后，我锁住生成的CRC并将其与在以太网帧中找到的CRC一起显示在LCD上。
Furthermore, I'm using a CRC32 generator from outputlogic.com. I aggregate the received nybbles to bytes and forward them to the CRC. At the end of the frame, I latch the generated CRC and display it on the LCD, together with the CRC I found in the ethernet frame.
但是，（
527edb0d -- FCS extracted from the frame
43a4d833 -- calculated using the CRC32 generator
第一个也可以通过通过pythons crc32函数运行程序包进行验证，
The first one can also be verified by running the package through pythons crc32 function, both with the frame captured by wireshark and the frame captured and retrieved via serial port from the FPGA.
我想这一定是微不足道的。 我在此处粘贴了接收过程。我剥离了所有不必要的东西。通过串行捕获输出时，我添加了一个fifo（Xilinx的现成产品），该器件与CRC生成器同时锁存，以获取完全相同的字节。
I guess it must be something more or less trivial. I pasted the receiving process over here. I stripped off everything which was not neccessary. When capturing the output via serial, I added a fifo (readily made unit from Xilinx) which latched at the same time as the CRC generator to get exactly the same bytes.
有人知道这有什么问题吗？
Does anyone have an idea what's wrong with that?
推荐答案
我不久前就开始使用以太网MAC，尽管我从未圆满完成它，我确实有一个可用的CRC生成器，可以在这里使用：
I started working on an ethernet MAC a while back, and although I never got round to finishing it I do have a working CRC generator that you can use here:
它基于IEEE 802.3上的Xilinx应用笔记CRC，您可以在此处。
Its based on a Xilinx App note on the IEEE 802.3 CRC, which you can find here.
CRC在
The CRC is instantiated in the ethernet receieve component, if you look at the ETH_RECEIVE_SM process you can see how the FCS is loaded into the checker.
希望您可以通过与我的代码进行比较来发现错误。
Hopefully you can spot your mistake by comparing with my code.
编辑：
我从 fpga4fun 并通过CRC检查器传递，请参见下面的模拟屏幕截图（右键单击，复制URL并在新的浏览器标签中查看以获取完整分辨率）：
I took the sample ethernet frame from fpga4fun and passed it through the CRC checker, see the simulation screenshot below (right click, copy URL and view in a new browser tab for full resolution):
您可以在最后看到剩余的 C704DD7B ，尝试使用自己的CRC检查器进行相同操作，然后查看得到的结果。
You can see the residual C704DD7B at the end there, try doing the same with your own CRC checker and see what you get.
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