生成if条件必须是一个常量表达式 [英] The generate if condition must be a constant expression
问题描述
我正在尝试为RISC-V程序集创建即时生成器，但是遇到了if语句. 这是我在Verilog中的代码:
module signextend(in, out, sel);
parameter nin = 32;
parameter nout = 32;
input [nin-1:nin-25] in;
input [2:0] sel;
output [nout-1:0] out;
if (sel == 3'b000)
begin
assign out[19:0] = in[31:12];
assign out[31:20] = {12{in[31]}};
end
else if (sel == 3'b001)
begin
assign out[11:0] = in[31:20];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b010)
begin
assign out[4:0] = in[24:20];
assign out[31:5] = 0;
end
else if (sel == 3'b011)
begin
assign out[3:0] = in[11:8];
assign out[4:9] = in[30:25];
assign out[10] = in[7];
assign out[11] = in[31];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b100)
begin
assign out[4:0] = in[11:7];
assign out[11:5] = in[31:25];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b101)
begin
assign out[9:0] = in[21:30];
assign out[10] = in[20];
assign out[18:11] = in[19:12];
assign out[19] = in[31];
assign out[31:20] = {12{in[31]}};
end
else
assign out = 32'hxxxx;
endmodule
每个if语句中都存在问题:generate if条件必须是一个常量表达式.
您需要将所有代码放入always块中，并删除assign s:
always @(*) begin
if (sel == 3'b000)
begin
out[19:0] = in[31:12];
out[31:20] = {12{in[31]}};
end
else if (sel == 3'b001)
// etc
always块包含一些软件(您的if语句)，该软件为一些硬件(生成的组合逻辑)建模. /p>
在always(或initial)块之外使用if语句是合法的，但这意味着有所不同.然后，这意味着有条件地包括硬件，即如果某些条件为真，则包括该硬件.这样的 condition 必须是 static ，即在编译时固定的.它不能是输入，例如您的sel.如果您考虑一下，那是完全有意义的:如何根据某些输入的值来创建一些可以神奇地出现和消失的硬件?你不能这就是为什么出现错误的原因.
您需要删除assign，因为在always块中包含assign是合法的，但这意味着有些奇怪.永远不要做.
I am trying to create an Immediate Generator for RISC-V assembly but I have encountered with if statement. Here is my code in Verilog:
module signextend(in, out, sel);
parameter nin = 32;
parameter nout = 32;
input [nin-1:nin-25] in;
input [2:0] sel;
output [nout-1:0] out;
if (sel == 3'b000)
begin
assign out[19:0] = in[31:12];
assign out[31:20] = {12{in[31]}};
end
else if (sel == 3'b001)
begin
assign out[11:0] = in[31:20];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b010)
begin
assign out[4:0] = in[24:20];
assign out[31:5] = 0;
end
else if (sel == 3'b011)
begin
assign out[3:0] = in[11:8];
assign out[4:9] = in[30:25];
assign out[10] = in[7];
assign out[11] = in[31];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b100)
begin
assign out[4:0] = in[11:7];
assign out[11:5] = in[31:25];
assign out[31:12] = {20{in[31]}};
end
else if (sel == 3'b101)
begin
assign out[9:0] = in[21:30];
assign out[10] = in[20];
assign out[18:11] = in[19:12];
assign out[19] = in[31];
assign out[31:20] = {12{in[31]}};
end
else
assign out = 32'hxxxx;
endmodule
The problem exists in each if statement: The generate if condition must be a constant expression.
You need to put all your code inside an always block and remove the assigns:
always @(*) begin
if (sel == 3'b000)
begin
out[19:0] = in[31:12];
out[31:20] = {12{in[31]}};
end
else if (sel == 3'b001)
// etc
An always block contains a little bit of software (your if statements) that models a little bit of hardware (the resulting combinational logic).
It is legal to have an if statement outside an always (or initial) block, but then it means something different. Then it means conditional including of hardware, ie if some condition is true, include this hardware. Such a condition has to be static, ie fixed at compile time. It cannot be an input, like your sel. If you think about it, that makes total sense: how could you create some hardware that magically appears and disappears depending on the value of some input? You can't. That is why you are getting your error.
You need to remove the assigns, because while it is legal to have an assign inside an always block, it means something weird. Never do it.
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