什么时候使用tick(')进行Verilog数组初始化? [英] When to use the tick(') for Verilog array initialization?

问题描述

可以在有或没有'的情况下完成数组初始化:

Array initialization can be done with or without the ':

int a[8] = '{0,1,2,3,4,5,6,7}; // Packed
int b[8] = {0,1,2,3,4,5,6,7};  // Unpacked

假设数组使用不可打包的类型(例如 int ， string 等)，是否有正确的方式?两种方法似乎都可以正常工作.

Is there a correct way, assuming the array uses an un-packable type like int, string, etc.? Both ways seem to work just fine.

EDA Playground上的完整代码示例: http://www.edaplayground.com/x/3Tc

Full code example on EDA Playground: http://www.edaplayground.com/x/3Tc

推荐答案

基于IEEE 1800-2009:

Based on IEEE 1800-2009:

数组分配模式(1)的优点是，可以通过在类型前面加上类型名称来使用它们来创建自定义类型的分配模式表达式.此外，可以使用诸如'{n {element}}之类的语法来复制分配模式中的项目，并可以使用default:语法将其作为默认值.但是，数组分配模式中的每个元素项都必须与目标数组的元素类型具有相同的类型.相比之下，解压缩数组串联(2)禁止复制，默认和显式键入，但是它们提供了从元素和数组的任意组合组成数组值的额外灵活性.

Array assignment patterns (1) have the advantage that they can be used to create assignment pattern expressions of selfdetermined type by prefixing the pattern with a type name. Furthermore, items in an assignment pattern can be replicated using syntax such as '{ n{element} }, and can be defaulted using the default: syntax. However, every element item in an array assignment pattern must be of the same type as the element type of the target array. By contrast, unpacked array concatenations (2) forbid replication, defaulting and explicit typing, but they offer the additional flexibility of composing an array value from an arbitrary mix of elements and arrays.

所以:

int A3[1:3];
int A9[1:9];

A3 = '{1, 2, 3}; #legal
A9 = '{3{A3}};   #illegal
A9 = {A3, 4, 5, A3, 6}; #legal
A9 = '{9{1}}; #legal
A9 = {9{1}}; #illegal

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