在波形的RTL层次的时钟块层次上的信号延迟 [英] Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform

问题描述

有一个testbench env，我正在做一些测试，我注意到在波形中，如果我从rtl层次中提取输入到rtl的特定信号，并从驱动器时钟模块中提取相同的信号，我会看到与在驱动时钟模块层次上的相同信号相比，在rtl层次上的信号延迟了一个时钟，而如果我拉出从rtl层次上的rtl输出的信号和在监视器时钟模块层次上的相同信号，则I看到相同的信号在监视器时钟块级别被延迟了一个周期.

There is a testbench env and I am working on some tests, I noticed that in the waveform if I pull a specific signal which is input to rtl from rtl hierarchy and pull the same signal from the driver clocking block, I see that the signal at rtl hierarchy is one clock delayed as compared to the same signal at the driving clocking block hierarchy while if I pull out a signal in waveform which is output from rtl at rtl hierarchy and the same signal at the monitor clocking block hierarchy, I see the same signal at monitor clocking block level is delayed by one cycle.

相对于在rtl层次结构中看到的信号，在监视器时钟模块级别的信号是否总是延迟并且在驱动器时钟模块级别的信号总是总是提前一个时钟?

Are the signals at monitor clocking block level always delayed and at driver clocking block level always come one clock early with respect to the signals seen at rtl hierarchy?

接口原型如下:

          interface my_if(input bit clk, bit reset);
             bit valid;
             bit [31:0] data;
             bit [2:0]  crdt; 

 
              clocking monitor_cb @(posedge clk); 
              default input #1 output #1; 
              input valid; 
              input data;
              input crdt;
              endclocking 

              clocking tx_driver_cb @(posedge clk); 
              default input #1 output #1; 
              output valid; 
              output data;
              input crdt;
              endclocking 

              clocking rx_driver_cb @(posedge clk); 
              default input #1 output #1; 
              input valid; 
              input data;
              output crdt;
              endclocking 
   
           modport tx_driver (clocking tx_driverv_cb);
           modport rx_driver (clocking rx_driver_cb);   
           modport monitor (clocking monitor_cb);

         endinterface

推荐答案

让我们以 monitor_cb.data 为例作为输入案例

Let's take the monitor_cb.data as an example for the input case

输入将被延迟#1 将在 clk 的上升沿进行采样.

The inputs will be delayed #1 will be sampled at the rising edge of clk.

// (pseudo code)
logic [31:0] skew_data;
assign #10 skew_data = my_if.data;
always @(posedge clk) begin
  monitor_cb.data <= skew_data;
end

如果您的信号在时钟的上升沿改变，则 sampled_data 将保留更新之前的值.

If your signal changes at the rising edge of the clock, the sampled_data will hold the value before the update.

现在输出的延迟是采样时刻而不是信号

Now for the outputs what is delayed is the sampling moment not the signal

always @(posedge clk) begin
  #1;
  tx_driver_cb.data <= data;
end

时钟后稍稍采样数据，因此对更新后的值进行采样.

The data is sampled slightly after the clock, so it samples the updated value.

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