MIPS中是否存在执行存储数据危险? [英] Is there an execute-store data hazard in MIPS?

问题描述

在具有流水线和转发功能的MIPS架构上:

On MIPS architecture with pipelining and forwarding:

add $s0, $t1, $t2
sw $s0, 0($sp)

加法指令将在第3步(执行操作)准备好结果，但是我假定sw指令在第2步需要结果(指令解码和寄存器读取).

The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read).

David A. Patterson在《计算机组织与设计》一书中有一个已解决的练习:在以下代码段中查找隐患，并对指令进行重新排序，以避免任何管线停顿:

There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls:

lw  $t1, 0($t0)
lw  $t2, 4($t0)
add $t3, $t1,$t2
sw  $t3, 12($t0)
lw  $t4, 8($01)
add $t5, $t1,$t4
sw  $t5, 16($t0)

解决方案:

lw  $t1, 0($t0)
lw  $t2, 4($t1)
lw  $t4, 8($01)
add $t3, $t1,$t2
sw  $t3, 12($t0)
add $t5, $t1,$t4
sw  $t5, 16($t0)

在解决方案中，它可以正确识别负载使用危险并相应地重新排列代码，但是是否也存在执行存储危险?

In the solution it correctly recognizes the load-use hazard and rearranges the code accordingly, but is there an execute-store hazard as well?

推荐答案

让我们考虑激活转发的MIPS.我认为在那种情况下不会发生危险:实际上，ADD指令是整数运算，在MIPS架构中仅需要一个时钟周期.看这张图:

Let's consider a MIPS in which forwarding is activated. I think that in that case no hazard occurs: in fact the ADD instruction is an integer operation that in the MIPS architecture requires only one clock cycle. Look at this graph:

ADD $t3,$t1,$t2    IF   ID   EX   MEM   WB
SW  $t3,12($t0)         IF   ID   EX    MEM  WB

您可以看到没有危险发生，因为SW指令在两个时钟周期后存储了数据，因为结果由ADD放入$ t3.

As you can see no hazard occurs because the SW instruction stores the datum after two clock cycles since the result is put in $t3 by ADD.

实际上，在类似情况下，也可能会发生危险，但前提是该单元是一个多周期单元(如果它需要多个时钟周期来计算数据).请看以下示例，其中ADD.D指令使用浮点加法器，该浮点加法器需要4个时钟周期来执行计算:

Actually in similar situations a hazard can occur but only if the unit is a multicycle one (if it requires more than one clock cycle to compute the data). Look ad this example, in which the ADD.D instruction uses a floating point adder that requires 4 clock cycles to perform the calculation:

ADD.D F2,F4,F5      IF   ID   A0   A1   A2   A3   MEM   WB
S.D   F2,somewhere       IF   ID   EX   X0   X1   X2    MEM    WB

X0和X1是RAW档，而X2是结构档:在前一种情况下，S.D必须等待ADD.D完成.在后者中，您的MIPS无法在相同的时钟周期内两次访问内存，因此会发生结构停顿.

X0 and X1 are RAW stalls while X2 is a structural stalls: in the former case S.D must wait for ADD.D to finish; in the latter your MIPS cannot access in the same clock cycle to the memory two times, so a structural stall occurs.

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