为什么"movnti"后面加上"sfence"可以保证持久的顺序? [英] Why “movnti” followed by an “sfence” guarantees persistent ordering？

问题描述

SFENCE防止NT存储从前面的存储缓冲区中提交SFENCE本身.

NT存储数据直接从存储缓冲区.

因此，SFENCE仅能保证进入LFB的数据的顺序.

Therefore SFENCE can only guarantees the ordering of data entering LFB.

例如，

movnti;
sfence;
movnti to another address;

此处的SFENCE只能保证第一个NT存储区将早于下一个NT存储区提交给LFB.但是，由于LFB是易失性的，因此数据尚未持久.进入LFB的数据是否会按照输入顺序持久保存?

The SFENCE here can only guarantees that the first NT store will be commit to LFB earlier than the next one. However, since LFB is volatile, the data has not been persisted yet. Will the data entering the LFB be persisted in the order of entering?

推荐答案

sfence 确保在程序顺序中的所有后续存储都变得全局可见之前，程序顺序中的所有较早存储都变得全局可见.这里的存储包括数据存储设备， clflush ， clflushopt ， clwb ， movdiri 和 movdir64b .

sfence ensures that all earlier stores in program order become globally observable before any later stores in program order become globally observable. Stores here include data store uops, clflush, clflushopt, clwb, movdiri, and movdir64b.

GO的要点取决于以下所有条件:

The point of GO depends on all of the following:

• 操作类型
• 非时间提示的存在
• 目标存储位置的存储类型
• 映射到目标内存地址的设备，并且
• 微体系结构.

例如，在现代的英特尔服务器处理器上，如果从内存中提取目标高速缓存行(如果内存中尚不存在)的情况下，不带NT提示的常规数据存储uop到达GO，而该NT提示的目标是映射到主内存的WB类型的内存位置.L1D处于适当的一致性状态，并且存储将提交给高速缓存.这就是为什么在异步DRAM刷新(ADR)平台(例如Intel CSX)上， sfence 本身不能保证持久性的原因.

For example, on a modern Intel server processor, a normal data store uop without the NT hint targeting a memory location of type WB mapped to main memory reaches GO when the target cache line is fetched from memory if not already present in the L1D in a suitable coherence state and the store is committed to the cache. That's why on an Asynchronous DRAM Refresh (ADR) platform such as Intel CSX, sfence by itself doesn't guarantee persistence.

关于您要询问的特定示例， movnti 是带有NT提示的数据存储指令.假设目标地址映射到ADR平台上的主存储器，则该指令的全局可观察性点与持久性域的第一点相同.因此，在任何具有NVDIMM的Intel或AMD平台上，无论内存类型如何，都可以保证在以后的任何存储变为持久存储之前，数据都位于持久存储域中.这比您所说的要强(保证 sfence 阻止以后的存储在先于先前的存储之前提交)，因为提交并不意味着持久性，但是持久性只能在提交之后发生.尽管在这里使用术语退休"可能更好.而不是提交"因为退休"是指在架构上是有意义的，并且指示改变线程的状态，但是提交"消息.是一个微体系结构操作，取决于设计.

Regarding the specific example you're asking about, movnti is a data store instruction with the NT hint. Assuming that the target address is mapped to main memory on an ADR platform, the point of global observability of this instruction is the same as the first point of the persistence domain. Therefore, on any Intel or AMD platform with NVDIMMs and regardless of the memory type, the data is guaranteed to be in the persistence domain before any later stores become persistent. This is a stronger guarantee than what you said (that sfence prevents later stores from committing before earlier stores) because commit doesn't imply persistence, but persistence can only happen after commit. Although it may be better here to use the term "retire" instead of "commit" because "retire" is meaningful architecturally and indicates changing the thread's state but "commit" is a microarchitectural operation and depends on the design.

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