多个目标但依存度相同 [英] Multiple targets but same dependency

问题描述

这是我的makefile的一部分:

This is a part of my makefile :

SRC     =   ./
DIRS    =   src libs/maths libs/struct
BIN_DIR =   ./bin/

SRC_DIRS=   $(foreach dir, $(DIRS), $(addprefix $(SRC), $(dir)))
SRC_TEST=   $(sort $(SRC_DIRS))

SRCS    =   $(foreach msrc, $(SRC_DIRS), $(wildcard $(msrc)/*.c))

DEL_PRE =   $(foreach target, $(SRCS), $(notdir $(target)))
ADD_PRE =   $(foreach target, $(DEL_PRE), $(addprefix $(BIN_DIR), $(target)))
OBJS    =   $(ADD_PRE:.c=.o)

.PHONY: all clean re

all:        $(EXEC)

$(EXEC):    $(OBJS)
    $(CC) $(OBJS) -o $@ $(LDLIBS)

$(OBJS):    $(SRCS)
    $(CC) -o $@ -c $<

当我使用make all时，我的输出是:

When i use make all, i have in output :

gcc -o bin/main.o -c src/main.c
gcc -o bin/cosin.o -c src/main.c
gcc -o bin/pears.o -c src/main.c
gcc -o bin/outil.o -c src/main.c
gcc -o bin/verif.o -c src/main.c

但是我想为每个目标分配一个依赖项:

But i would like to have for each target, it assigned dependency :

gcc -o bin/main.o -c src/main.c
gcc -o bin/cosin.o -c libs/maths/cosin.c
gcc -o bin/pears.o -c libs/maths/pears.c
gcc -o bin/outil.o -c libs/struct/outil.c
gcc -o bin/verif.o -c libs/struct/verif.c

我该如何解决?

推荐答案

这似乎是一种非常普遍的误解；我昨天刚刚有效地回答了同样的问题.我不确定它来自哪里或如何抵抗它.

This seems like a very common misconception; I just answered effectively this same question yesterday. I'm not sure where it comes from or how to combat it.

此规则:

$(OBJS):    $(SRCS)
       $(CC) -o $@ -c $<

不会以某种方式神奇地组合 OBJS 变量和 SRCS 变量的内容来弄清楚它们如何匹配.变量引用被简单地扩展，结果是这样的:

does not somehow magically combine the contents of the OBJS variable and the SRCS variable to figure out how they match up. The variable references are simply expanded, and the result is this:

bin/main.o bin/cosin.o ... : src/main.c libs/maths/cosin.c ...
       $(CC) -o $@ -c $<

这与您编写此代码相同:

which is the same as if you'd written this:

bin/main.o : src/main.c libs/maths/cosin.c ...
       $(CC) -o $@ -c $<
bin/cosin.o : src/main.c libs/maths/cosin.c ...
       $(CC) -o $@ -c $<
...

现在，您可以希望看到为什么要编译相同的文件:在每条规则中您都具有相同的先决条件，因此 $< 始终是第一个，而始终是 src/main.c .

Now, you can hopefully see why you compile the same file: in every rule you have the same prerequisites, so $< is always the first one, which is always src/main.c.

有多种方法可以解决此问题，但是，如果您确实希望将来自不同目录的所有源文件编译为同一目录中的目标文件，则您的工作会比较困难，因为没有通用的模式可以将它们全部匹配.在这种情况下，最简单的方法是使用 VPATH进行目录搜索:将上述规则替换为:

There are multiple ways to work this but if you really want to have all the source files from different directories compiled into object files in the same directory your job is harder, because there's no common pattern that will match them all. In this case the simplest thing to do is use VPATH for directory search: replace the above rule with this:

$(BIN_DIR)/%.o : %.c
       $(CC) -o $@ -c $<

然后告诉make如何找到您的源文件，像这样:

then tell make how to find your source files, like this:

VPATH := $(sort $(dir $(SRCS))

请注意，此方法不能用于任何本身会生成预期由make创建的输出的源文件.

Be aware this method can't be used for any source files that are themselves generated output that make is expected to create.

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