什么是VHDL中的#define等效项 [英] what is #define equivalent in VHDL

问题描述

在VHDL中，#define，#ifdef和#ifndef等效于什么?

what is the equivalent of #define, #ifdef and #ifndef in VHDL?

我想将泛型用作#define，并根据它们更改设计.举一个简单的例子:定义一个通用字符串，并用它来确定时钟是单时钟还是差分时钟.

I want to use generics as #define, and change the design according to them. as a simple example: define a string generic and use it to determine if the clock is single or differential.

generic (
  something : boolean := FALSE;
  CLK_MODE : string := "SINGLE_ENDED"
);

现在，如何根据泛型更改逻辑?一个人当然可以用一个简单的if语句编写2种可能的逻辑描述，但随后两者都将被合成(尽管实际上只使用了一个).

Now, How to change the logic according to the generics? one can of course write 2 possible logic descriptions with a simple if statement but then both will be synthesized (although only one is really used).

此外，是否可以根据通用名称更改端口?对于CLK示例，差分时钟需要2个端口，但单端时钟仅需要1个.如何根据通用端口启用或禁用第二个端口?

Also, Is it possible to change the ports according to the generic? for the CLK example, 2 in ports are needed for differential clock but only one is needed for single ended clock. how to enable or disable the second port according to the generic?

推荐答案

一种根据条件合成不同硬件电路的方法是使用 generic 和 if-generate 声明.在下面的示例中，当通用 ARITHMETIC_OPERATION_IS_ADD 为true时，将生成一个加法器.如果为假，则会生成一个减法器.

One way to synthesize different hardware circuits depending on a condition is using a generic with an if-generate statement. In the example below, when the generic ARITHMETIC_OPERATION_IS_ADD is true, an adder is generated. When it is false, a subtractor is generated.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity conditional_hardware is
    generic (
        ARITHMETIC_OPERATION_IS_ADD: boolean := true
    );
    port (
        a, b: in unsigned(7 downto 0);
        y: out unsigned(7 downto 0)
    );
end;

architecture example of conditional_hardware is
begin

    adder: if ARITHMETIC_OPERATION_IS_ADD generate
        y <= a + b;
    end generate;

    subtractor: if not ARITHMETIC_OPERATION_IS_ADD generate
        y <= a - b;
    end generate;

end;

注意:如果您确实想要它，可以使用VHDL预处理程序，它们的功能与C ++相似.例如，看看 http://vhdlpp.sourceforge.net/README .

Note: if you really want it, there are VHDL preprocessors that work much as their C++ counterparts. For instance, take a look at http://vhdlpp.sourceforge.net/README.

要很好地全面介绍可重用VHDL的基础知识，我强烈推荐VLSI Technology的白皮书

For a very good and comprehensive introduction to the fundamentals of reusable VHDL, I highly recommend VLSI Technology's whitepaper Coding Tips and Techniques for Synthesizeable, Reusable VHDL.

自从我上次使用LVDS已经有一段时间了，因此以下内容可能已过时.对于输出，您可以为两个输出引脚分配互补值:

It's been a while since I last used LVDS, so the following may be out of date. For outputs, you can assign complementary values to two output pins:

diff_out_p <= my_signal;
diff_out_n <= not my_signal;

然后，在项目设置文件上，将它们分配给差分对，并将输出标准设置为LVDS或您使用的任何值.

Then, on your project settings file, assign them to a differential pair, and set the output standard to LVDS or whatever you use.

对于输入，我的工具手册建议实例化原语.该原语有两个输入和一个输出.您应该将输入连接到差分对，并在您的VHDL代码(在下面的示例中为< data_out> )中使用输出.

For inputs, my tool manual recommends instantiating a primitive. This primitive has two inputs and one output. You should connect the inputs to a differential pair, and use the output in your VHDL code (<data_out> in the example below).

library altera; 
use altera.altera_primitives_components.all; 

lvds_input_buffer : ALT_INBUF_DIFF
generic map (
    IO_STANDARD => "LVDS",
    LOCATION => "IOBANK_1A",
    ENABLE_BUS_HOLD => "off",
    WEAK_PULL_UP_RESISTOR => "off"
)  port map ( 
    i => <data_in_pos>,
    ibar => <data_in_neg>,
    o => <data_out>
);

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