CR8寄存器如何用于对x86-64 CPU中的中断进行优先级排序? [英] How is CR8 register used to prioritize interrupts in an x86-64 CPU?
问题描述
我正在阅读有关控制寄存器的英特尔文档，但仍在努力了解如何使用CR8寄存器.引用文档(
I'm reading the Intel documentation on control registers, but I'm struggling to understand how CR8 register is used. To quote the docs (2-18 Vol. 3A):
任务优先级(CR8的位3:0)—设置阈值对应于要阻止的最高优先级中断.一种值为0表示所有中断均被使能.该字段可用在64位模式下.值15表示将禁止所有中断.
Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corresponding to the highest- priority interrupt to be blocked. A value of 0 means all interrupts are enabled. This field is available in 64- bit mode. A value of 15 means all interrupts will be disabled.
如果您不介意的话，我有3个快速问题:
I have 3 quick questions, if you don't mind:
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因此，CR8的位3至0构成了这16个优先级值.但是优先级是什么?我认为正在运行的线程"对吗?
So bits 3 thru 0 of CR8 make up those 16 levels of priority values. But priority of what? A running "thread", I assume, correct?
但是与接收中断以查看是否必须阻止该中断相比，CR8中的优先级值是多少?
But what is that priority value in CR8 compared to when an interrupt is received to see if it has to be blocked or not?
当中断被阻止时，这意味着什么?是延迟"到以后，还是只是被丢弃，即丢失了?
When an interrupt is blocked, what does it mean? Is it "delayed" until later time, or is it just discarded, i.e. lost?
推荐答案
CR8指示CPU的当前优先级.当中断待处理时，将中断向量号的位7:4与CR8进行比较.如果向量较大，则将对其进行维修，否则将其保持待处理状态，直到将CR8设置为较低的值为止.
CR8 indicates the current priority of the CPU. When an interrupt is pending, bits 7:4 of the interrupt vector number is compared to CR8. If the vector is greater, it is serviced, otherwise it is held pending until CR8 is set to a lower value.
假设使用APIC，它具有一个IRR(中断请求寄存器)，每个中断向量号各一位.将该位置1时，中断将挂起.它可以永远保持这种状态.
Assuming the APIC is in use, it has an IRR (Interrupt Request Register) with one bit per interrupt vector number. When that bit is set, the interrupt is pending. It can stay that way forever.
当中断到达时，将其与IRR进行或运算.如果该中断已经挂起(即该向量的IRR位已被设置)，则新中断将与前一个中断合并.(您可以说它已被删除，但我不这么认为；相反，我说这两个被合并为一个.)由于这种合并，中断服务例程必须被设计为处理所有准备好的工作.，而不是期望每个工作单元都有明显的中断.
When an interrupt arrives, it is ORed into the IRR. If the interrupt is already pending (that is, the IRR bit for that vector is already set), the new interrupt is merged with the prior one. (You could say it is dropped, but I don't think of it that way; instead, I say the two are combined into one.) Because of this merging, interrupt service routines must be designed to process all the work that is ready, rather than expecting a distinct interrupt for each unit of work.
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