RISC-V中断处理流程 [英] RISC-V Interrupt Handling Flow

问题描述

我正在寻找RISC-V处理器如何处理中断请求.

我查看了《指令集手册》和互联网上的信息.重点在于准确解释标题设置的内容:指令集.在我看来，如何处理中断是一个问题，即所谓的处理器程序员模型".由于中断处理的某些部分未在指令中表达，因此它显然不适合有关指令集的文档.显然，进入ISR不是 一条显示在程序代码中任何地方的指令.指令集手册提供了诸如 mret 和 mstatus 的描述，但未能提供整体视图.

对于一个假设的体系结构，中断处理可以这样描述:

 如果IRQ线为高电平并且状态寄存器中的I位已设置，处理器自动执行以下步骤:-将下一条指令的PC推入堆栈.-将状态寄存器压入堆栈.-清除状态寄存器中的I位.-PC设置在INTHNDLR寄存器中指定的位置. 

这是我正在寻找的RISC-V体系结构的信息.

解决方案

从根本上说，处理器具有一些额外的寄存器，称为控制和控制".状态寄存器(也称为CSR)，用于保存一些关键状态，例如被中断的pc，被中断的特权级别以及中断的原因等.此外，CSR保留中断配置，其状态之一是中断向量表的地址以及当前特权级别，以及其他状态，例如它是否以32位模式或更高版本运行./p>

在中断时，处理器的全部工作就是

• 将中断的计算机捕获到CSR中-称为 mepc
• 将当前特权级别捕获到CSR中
• 设置中断原因CSR-称为 mcause
• 如果异常是由于页面错误引起的，则 mtval 保留错误地址
• 关闭中断- mie
• 在CSR指定的向量表中查找中断处理程序—称为 mtvec
• 并将转移控制(设置PC)到ISR

在RISC V中，使规范变得非常复杂的是特权规范中可选事物的数量.其中有3个CSR库(CSR名称的首字母不同)—与3个特权级U，S，M松散相关联—其中大多数是可选的(实际上只需要M).(例如，也是可选的，可以是64位或更大的(128)，并且可以在32位模式下运行，具有多个处理器，浮点数等.)

这里有CRS库和特权级别，因此完整的实施可以为管理程序/虚拟机，操作系统和应用程序提供良好的支持.例如，对于一个简单的应用程序，在嵌入式处理器上，实际上只需要一个CSR库和一个特权级别.

如果您熟悉MIPS中断处理，您会发现RISC V有点熟悉，尽管复杂得多.但是，从根本上讲，这些处理器使用额外的寄存器(在MIPS上，它们位于协处理器0"中)，而不是使用堆栈来存储中断状态.MIPS将2个通用处理器寄存器(整数 $ k0 ， $ k1 )专用于中断处理，而RISC V则没有.但是，与MIPS不同，RISC V为中断处理程序提供了额外的CSR以供使用，称为 mscratch ，可用于(例如 $ k0 )来临时保存来自中断处理程序的值.ISR的正常寄存器(被中断线程的)，或者由于ISR受保护，可以将其设置为指向当前运行线程的控制块的指针，可以在其中保存被中断线程的CPU寄存器.

RARS模拟器提供U和M两种模式，并具有M套CSR，可让您将中断处理程序编写为迷你操作系统来为应用程序提供服务.

如果您想了解更多信息，请从研究MRET指令开始，因为这会稍微反转/取消中断.否则，请查看RARS模拟器，您可以在其中实际编写中断处理程序.

I am looking for how a RISC-V processor processes interrupt requests.

I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title sets: the instruction set. In my view, how interrupts are handled is a question of what is called the "programmer's model" of the processor. It does not clearly fit into a document about an instruction set, because parts of interrupt processing are not expressed in instructions. Clearly, jumping into an ISR is not an instruction that shows up anywhere in the program code. The Instruction Set Manuals offer descriptions of say mret and mstatus, but fail to provide a holistic view.

For a hypothetical architecture, interrupt processing might be described like this:

If the IRQ line is high and the I-bit in the status register is set,
the processor executes the following steps atomically:

 - Push the PC of the next instruction onto the stack.
 - Push the status register onto the stack.
 - Clear the I-bit in the status register.
 - The PC is set to the location specified in the INTHNDLR register.

This is the kind of information I am looking for for the RISC-V architecture.

解决方案

Fundamentally, the processor has some extra registers, called Control & Status Registers, aka CSRs, that are used to hold some critical state, such as the interrupted pc, the interrupted privilege level, and the cause of the interrupt, etc...  In addition, the CSR's hold the interrupt configuration, one piece of state of which is the address of the interrupt vector table, as well as the current privilege level, and more, like whether it is running in 32-bit mode or larger.

Upon an interrupt, all the processor does then, is

• capture the interrupted pc into a CSR — called mepc
• capture the current privilege level into a CSR
• set the interrupt cause CSR — called mcause
• if the exception was due to a page fault then mtval holds the fault address
• turn off interrupts — mie
• look up the interrupt handler in the vector table specified by a CSR — called mtvec
• and transfer control (set the pc) to the ISR

Significantly complicating things in RISC V is the number of optional things in the privileged specification.  Among them there are 3 banks of CSR's (the CSR names vary the first letter) — loosely associated with the 3 allowed for privilege levels, U, S, M — most of which are optional (only M is actually required).  (Also optional, for example, is 64-bit or larger (128), and the ability to then run in a 32-bit mode, multiple processors, floating point, etc..)

The CRS banks and privilege levels are there so that a complete implementation can provide good support for hypervisors/virtual machines, operating systems, and applications.  For a simple application, say, on an embedded processor, only one CSR bank and one privilege level are really needed.

If you are familiar with MIPS interrupt handling, you'll find RISC V somewhat familiar though quite a bit more complicated.  However, fundamentally, these processors use extra registers (on MIPS they are in "coprocessor 0") rather than stack for storage of interrupted state.  Whereas MIPS dedicated 2 of the general purpose processor registers (integer $k0, $k1) to interrupt handling, RISC V does not.  However, unlike MIPS, RISC V provides an additional CSR for interrupt handlers to use — called mscratch, which can be used (like $k0) to temporarily hold a value from a regular register (of the interrupted thread) for the ISR to function, or, because it is protected, it can be set up as a pointer to the currently running thread's control block, where CPU registers of the interrupted thread can be saved.

The RARS simulator provides for two modes, U and M, and has the M set of CSR's, which allow you to write an interrupt handler as a mini operating system to service an application.

If you want more information, start with study of the MRET instruction, since this somewhat reverses/undoes the interrupt.  Otherwise, have a look at the RARS simulator where you can actually write an interrupt handler.

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