性能如何使用离线事件? [英] How does perf use the offcore events?

问题描述

一些内置的 perf 事件被映射到非核心事件.例如， LLC-loads 和 LLC-load-misses 被映射到 OFFCORE_RESPONSE.事件.如此处所述，可以很容易地确定这一点.但是，这些脱机事件需要将某些值写入某些MSR寄存器以实际指定特定事件. perf 似乎正在使用一个名为

Some built-in perf events are mapped to offcore events. For example, LLC-loads and LLC-load-misses are mapped to OFFCORE_RESPONSE. events. This can be easily determined as discussed in here. However, these offcore events require writing certain values to certain MSR registers to actually specify a particular event. perf seems to be using an array called something like snb_hw_cache_extra_regs to specify what values to write to which MSR registers. I would like to know how this array is used. Basically I want to know how to determine the specific offcore event that a perf event is mapped to by looking at the source code.

推荐答案

脱机PM MSR的阵列存储

The array of the offcore PM MSRs is stored here for SnB, other architectures are close.
The macro INTEL_UEVENT_EXTRA_REG is here and it just sets the msr to the second parameter, the config_mask to 0x000000FFULL and the valid_mask to the third parameter (the first being the event to program the the associated ordinary PMR with).

snb_hw_cache_extra_regs 的值就是将要写入所选PM MSR ¹ 的值.
在此处查找该数组a>和使用在此处中选择第一次PM MSR匹配，其中 config arg来自数组

The values of the snb_hw_cache_extra_regs is just what it's going to be written in the selected PM MSR¹.
This array is looked up here and used here to select the first PM MSR matching, where the config arg comes from the array hw_cache_event_ids.

因此，基本上是一个循环测试几个位掩码，直到找到兼容的PM MSR，我认为您可以跳过该过程，然后查看存储在 snb_hw_cache_extra_regs 数组中的值.

So it's basically a loop testing a couple of bitmasks until a compatible PM MSR is found, I think you can just skip that and look at the values stored in the snb_hw_cache_extra_regs array.

¹ 由于定义为使 snb_hw_cache_extra_regs 中的值的宏从未在源代码中重复使用，并且这些值直接映射到Intel手册中记录的MSR布局，因此我不必费心验证此语句.

¹ Since the macro defined to make the values in snb_hw_cache_extra_regs are never reused in source and the values maps directly to the MSR layout documented in the Intel manuals, I didn't bother verifying this statement.

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