systemverilog 模块命名空间 [英] systemverilog module namespaces

问题描述

我将两种设计组合成一个单芯片设计.RTL 代码是用 SystemVerilog 编写的，用于综合.不幸的是，这两种设计包含许多名称相同但逻辑略有不同的模块.

I am combining two designs into a single chip design. The RTL code is written in SystemVerilog for synthesis. Unfortunately, the two designs contain a number of modules with identical names but slightly different logic.

SystemVerilog 中是否有名称空间或库功能允许我指定具有相同名称的不同模块?换句话说，我可以使用 lib1::module1, lib2::module1 语法来指定我想要的模块吗?如何最好地处理这种模块命名空间污染?

Is there a namespace or library capability in SystemVerilog that would allow me to specify different modules with the same name? In other words is there a lib1::module1, lib2::module1 syntax I could use to specify which module I want? How is this sort of module namespace pollution best handled?

谢谢

推荐答案

查看 config 和 library.请参阅IEEE Std 1800-2017 §33. 配置设计内容

Look into config and library. See IEEE Std 1800-2017 § 33. Configuring the contents of a design

library 将根据文件路径将此文件映射到目标库 (IEEE Std 1800-2017 § 33.3.图书馆)
config 将映射用于瘫痪模块(全局、实例、子范围)的库(IEEE Std 1800-2017 § 33.4.配置)

library will map this files to target libraries based on file paths (IEEE Std 1800-2017 § 33.3. Libraries)
config will map which library to use for paralytic module (global, instances, subscope) (IEEE Std 1800-2017 § 33.4. Configurations)

示例在第 33.8 节中提供.
注意:一些模拟器需要在命令行中使用 -libmap .请参阅您的模拟器手册.

Examples are provided in the section 33.8.
Note: some simulators want -libmap <configfile> in the command line. Refer to your simulators manual.

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