System Verilog fork join - 实际上不是并行的? [英] System Verilog fork join - Not actually parallel?
问题描述
我正在学习系统 verilog,并认为在 fork/join
中为每个进程创建了单独的线程.但是,我发现如果我的第一个进程中有一个 while
循环,我的第二个进程不会启动,这让我觉得 fork/join
实际上不是并行的.>
I am learning system verilog and thought separate threads are created for each process in fork/join
. But, I find if I have a while
loop in my first process, my second process does not start, which makes me think fork/join
is not actually parallel.
class A;
task run();
$display("A started");
while(1);
endtask
endclass
class B;
task run();
$display("B started");
endtask
endclass
class C;
task run();
fork
A.run();
B.run();
join
endtask
endclass
我的输出是
Class A started
并且程序永远运行.我认为它应该打印
and the program is running forever. I thought it should print
Class A started
Class B started
并永远运行.有人可以指出我在这里缺少什么吗?
and run forever. Could someone point out what I am missing here?
推荐答案
SystemVerilog fork/join
语句创建仅在模拟意义上并行的进程.但是,进程在多核意义上不是并行的——进程不会在处理器的多个线程上执行.这些进程将在相同的模拟时间戳上安排在执行队列上.但是,这些将在单个逻辑 CPU 上执行,因此,从 CPU 的角度来看,它们将按顺序执行.
SystemVerilog fork/join
statement creates processes that are parallel only in the simulation sense. But, the processes are not parallel in the multicore sense -- the processes will not be executed on multiple threads of a processor. These processes would be scheduled on the execution queue at the same simulation time stamp. But, these would be executed on a single logical CPU, and therefore, from the CPU perspective, they would be executed sequentially.
在您的代码示例中,A 类和 B 类 run
任务计划在同一模拟时间执行.当 SystemVerilog 模拟器遇到 fork/join
语句时,它会将它们放在执行队列中.当您运行模拟时,您的模拟器首先启动 A.run
.并且由于 A.run
进程进入一个不会让步的无限循环,模拟器没有机会执行 B.run
.请注意,如果您在同一仿真时间安排了多个任务,SystemVerilog LRM 不会规定首先执行哪个任务.某些其他模拟器可能在启动 A.run
之前执行了 B.run
.
In your code example, both class A and B run
tasks are scheduled to be executed at the same simulation time. When the SystemVerilog simulator comes across the fork/join
statement, it puts them on the execution queue. When you ran the simulation, your simulator started A.run
first. And since A.run
process goes into an infinite loop that does not yield, the simulator did not get a chance to execute B.run
. Note that if you have multiple tasks scheduled at the same simulation time, the SystemVerilog LRM does not dictate which task would be executed first. Some other simulator might have executed B.run
before starting A.run
.
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