VHDL:使用 inout 端口是不好的做法吗? [英] VHDL: is using inout port bad practise?

问题描述

我有一个程序，我使用以下方式使用 inout 端口:

I have a program where i'm using inout port following way:

port : inout unsigned(9 downto 0);
...
if port > 10 then
   port <= port + 1
end if;

我正在使用 inout 端口，所以我可以读取输出(实现反馈).

I'm using inout port so i can read output (to realize feedback).

要么是我和老师之间有误会，要么是我的老师强烈反对使用 inout 端口.

Either there was missunderstanding between me and my teacher, or my teacher is strongly against using inout ports.

我已经习惯了高级编程，所以写这样的代码对我来说并不奇怪.我知道 FPGA 上没有多少带有 inout 端口的电路，但是我不经常使用它，将 inout 端口拆分为 in 和 out 只是为了获得我想要的功能，这与我的感觉相反，不同的方式.

我很高兴您对使用 inout 端口的第二意见.

推荐答案

如果你正在实现一个双向端口，那么当然使用 inout 是正确的！

If you are implementing a bidirectional port, then of course inout is the right thing to use!

但是对于读取您输出到端口的值，您的老师是对的；这是非常糟糕的做法.(如果其他东西也在驱动该端口，您将看到解析值而不是您想要的值).

BUt for reading the value you are outputting to a port, your teacher is right; it is extremely bad practice. (If something else is also driving that port you will see the resolved value instead of the value you want).

这就是缓冲"端口的用途.

That is what "buffer" ports are for.

不幸的是，对缓冲端口有很多奇怪的偏见，一些工具在你使用它们时会发出不必要的警告(尽管它们通常实现得很好！)并且有一些不必要的奇怪规则将缓冲端口连接到外部模块中的端口.

Unfortunately there has been a lot of odd prejudice against buffer ports, and some tools warn unnecessarily when you use them (though they usually implement them just fine!) and there are some unnecessarily odd rules connecting buffer ports to ports in outer modules.

我不记得确切的细节，但我相信缓冲端口不能直接连接到下一级的输出端口 - 尽管 VHDL-2002 和更新版本删除了这个规则.尽管缓冲"端口现在更容易使用，但仍有一些人不愿意使用它们.

I can't remember exact details but I believe a buffer port can't connect directly to an output port in the next level up - though VHDL-2002 and newer removed this rule. Even though "buffer" ports are now more readily usable, there is still some reluctance to use them.

因此，最常见的解决方案是使用内部信号，例如port_int 可以读取，还有一个简单的赋值语句将其复制到实际端口.

As a result of all this, the commonest solution is to use an internal signal e.g. port_int which you can read, and a simple assignment statement to copy it to the actual port.

因此，VHDL-2008 取消了禁止读取被驱动到输出"端口的值的限制，使输出"端口与缓冲区"端口无法区分.

So VHDL-2008 has removed the restriction prohibiting reading the value being driven to an "out" port, making an "out" port indistinguishable from a "buffer" port.

我的偏好:使用缓冲端口.

My preference : use a Buffer port.

如果有某种原因阻止了这一点(比如代码风格指南或当地流行的意见)，那么(a) 如果您的工具支持 VHDL-2008 或(b) 使用内部信号.

If there is some reason preventing this (say a code style guide, or local prevailing opinion), then (a) use "out" ports if your tools support VHDL-2008 or (b) use an internal signal.

这篇关于VHDL:使用 inout 端口是不好的做法吗?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！